Decode: Set correct rpc for coprocessor register transfer.
[firearm.git] / system.v
index a0c35d6..b8fc48e 100644 (file)
--- a/system.v
+++ b/system.v
@@ -63,6 +63,13 @@ module System(input clk);
        wire [3:0] memory_out_write_num;
        wire [31:0] memory_out_write_data;
        
+       wire cp_req;
+       wire cp_ack = 0;
+       wire cp_busy = 0;
+       wire cp_rnw;
+       wire [31:0] cp_read = 0;
+       wire [31:0] cp_write;
+       
        wire stall_cause_issue;
        wire stall_cause_execute;
        wire stall_cause_memory;
@@ -157,6 +164,8 @@ module System(input clk);
        Memory memory(
                .clk(clk), .Nrst(1'b0),
                /* stall? flush? */
+               .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
+               .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
                .st_read(regfile_read_3), .st_data(regfile_rdata_3),
                .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
                .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
@@ -164,7 +173,8 @@ module System(input clk);
                .outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
                .outpc(pc_out_memory), .outinsn(insn_out_memory),
                .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
-               .out_write_data(memory_out_write_data));
+               .out_write_data(memory_out_write_data),
+               .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write));
 
        reg [31:0] clockno = 0;
        always @(posedge clk)
This page took 0.017334 seconds and 4 git commands to generate.