Merge Memory.

[firearm.git] / system.v

diff --git a/system.v b/system.v
index 4a485c3d1b81d3fde028e9fbcaef936bc4e7d5d3..da9d7017b58227bf5d2d2bfc5e1a6c28b6a48e2a 100644 (file)
--- a/system.v
+++ b/system.v
@@ -1,4 +1,5 @@
 `define BUS_ICACHE 0
+`define BUS_DCACHE 1
 
 module System(input clk);
        wire [7:0] bus_req;
@@ -9,23 +10,30 @@ module System(input clk);
        wire bus_rd, bus_wr;
        wire bus_ready;
 
-       wire bus_req_icache;    
-       assign bus_req = {7'b0, bus_req_icache};
+       wire bus_req_icache;
+       wire bus_req_dcache;
+       assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
        wire bus_ack_icache = bus_ack[`BUS_ICACHE];
+       wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
        
        wire [31:0] bus_addr_icache;
        wire [31:0] bus_wdata_icache;
        wire bus_rd_icache;
        wire bus_wr_icache;
        
+       wire [31:0] bus_addr_dcache;
+       wire [31:0] bus_wdata_dcache;
+       wire bus_rd_dcache;
+       wire bus_wr_dcache;
+       
        wire [31:0] bus_rdata_blockram;
        wire bus_ready_blockram;
        
-       assign bus_addr = bus_addr_icache;
+       assign bus_addr = bus_addr_icache | bus_addr_dcache;
        assign bus_rdata = bus_rdata_blockram;
-       assign bus_wdata = bus_wdata_icache;
-       assign bus_rd = bus_rd_icache;
-       assign bus_wr = bus_wr_icache;
+       assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
+       assign bus_rd = bus_rd_icache | bus_rd_dcache;
+       assign bus_wr = bus_wr_icache | bus_wr_dcache;
        assign bus_ready = bus_ready_blockram;
 
        wire [31:0] icache_rd_addr;
@@ -33,6 +41,11 @@ module System(input clk);
        wire icache_rd_wait;
        wire [31:0] icache_rd_data;
        
+       wire [31:0] dcache_addr;
+       wire dcache_rd_req, dcache_wr_req;
+       wire dcache_rw_wait;
+       wire [31:0] dcache_wr_data, dcache_rd_data;
+       
        wire stall_cause_issue;
        wire stall_cause_execute;
        
@@ -40,7 +53,6 @@ module System(input clk);
        wire decode_out_carry;
        wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
        wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
-       wire execute_out_stall, execute_out_bubble;
        wire execute_out_write_reg;
        wire [3:0] execute_out_write_num;
        wire [31:0] execute_out_write_data;
@@ -49,14 +61,15 @@ module System(input clk);
        
        wire bubble_out_fetch;
        wire bubble_out_issue;
+       wire bubble_out_execute;
        wire [31:0] insn_out_fetch;
        wire [31:0] insn_out_issue;
+       wire [31:0] insn_out_execute;
        wire [31:0] pc_out_fetch;
        wire [31:0] pc_out_issue;
+       wire [31:0] pc_out_execute;
 
-       wire execute_outflush = jmp;
-       wire issue_flush = execute_outflush;
-       wire execute_flush = 1'b0;
+       wire execute_out_backflush;
 
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
@@ -70,6 +83,15 @@ module System(input clk);
                .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
                .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
        
+       DCache dcache(
+               .clk(clk),
+               .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
+               .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
+               .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
+               .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
+               .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
+               .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
+
        BlockRAM blockram(
                .clk(clk),
                .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
@@ -88,7 +110,7 @@ module System(input clk);
        Issue issue(
                .clk(clk),
                .Nrst(1'b1 /* XXX */),
-               .stall(stall_cause_execute), .flush(issue_flush),
+               .stall(stall_cause_execute), .flush(execute_out_backflush),
                .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
                .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
                .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
@@ -110,15 +132,16 @@ module System(input clk);
        
        Execute execute(
                .clk(clk), .Nrst(1'b0),
-               .stall(1'b0 /* XXX */), .flush(execute_flush),
+               .stall(1'b0 /* XXX */), .flush(1'b0),
                .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
                .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
                .op2(decode_out_op2), .carry(decode_out_carry),
-               .outstall(stall_cause_execute), .outbubble(execute_out_bubble),
+               .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
                .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
                .write_data(execute_out_write_data),
-               .jmppc(jmppc),
-               .jmp(jmp));
+               .jmp(jmp), .jmppc(jmppc),
+               .outpc(pc_out_execute), .outinsn(insn_out_execute));
+       assign execute_out_backflush = jmp;
 
        reg [31:0] clockno = 0;
        always @(posedge clk)
@@ -128,6 +151,6 @@ module System(input clk);
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
                $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
-               $display("%3d: EXEC:   Stall: %d, Bubble: %d, Output: %d, [%08x -> %d]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num);
+               $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
        end
 endmodule