- 32'b????000000??????????????1001????: begin /* Multiply */
- regsel0 = insn[15:12]; /* Rn */
- regsel1 = insn[3:0]; /* Rm */
- regsel2 = insn[11:8]; /* Rs */
- op1_res = regs1;
- new_cps = cps_in;
- end
-/*
- 32'b????00001???????????????1001????: begin * Multiply long *
- regsel0 = insn[11:8]; * Rn *
- regsel1 = insn[3:0]; * Rm *
- regsel2 = 4'b0; * anyus *
- op1_res = regs1;
- end
-*/
- 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
- new_cps = cps_in;
- end
- 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
- new_cps = cps_in;
- end
- 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
- new_cps = cps_in;
- end
- 32'b????00??????????????????????????: begin /* ALU */
- regsel0 = insn[19:16]; /* Rn */
- regsel1 = insn[3:0]; /* Rm */
- regsel2 = insn[11:8]; /* Rs for shift */
+ `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+ begin
+ read_0 = insn[15:12]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ read_2 = insn[11:8]; /* Rs */
+
+ op0_out = regs0;
+ op1_out = regs1;
+ op2_out = regs2;
+ end
+// `DECODE_ALU_MUL_LONG: /* Multiply long */
+// begin
+// read_0 = insn[11:8]; /* Rn */
+// read_1 = insn[3:0]; /* Rm */
+// read_2 = 4'b0; /* anyus */
+//
+// op1_res = regs1;
+// end
+ `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
+ begin end
+ `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
+ begin
+ read_0 = insn[3:0]; /* Rm */
+
+ op0_out = regs0;
+ end
+ `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ begin
+ read_0 = insn[3:0]; /* Rm */
+
+ if(insn[25]) begin /* the constant case */
+ op0_out = rotate_res;
+ end else begin
+ op0_out = regs0;
+ end
+ end
+ `DECODE_ALU_SWP: /* Atomic swap */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+
+ op0_out = regs0;
+ op1_out = regs1;
+ end
+ `DECODE_ALU_BX: /* Branch and exchange */
+ begin
+ read_0 = insn[3:0]; /* Rn */
+
+ op0_out = regs0;
+ end
+ `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
+ begin
+ read_0 = insn[19:16];
+ read_1 = insn[3:0];
+
+ op0_out = regs0;
+ op1_out = regs1;
+ end
+ `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
+ begin
+ read_0 = insn[19:16];
+
+ op0_out = regs0;
+ op1_out = {24'b0, insn[11:8], insn[3:0]};
+ end
+ `DECODE_ALU: /* ALU */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ read_2 = insn[11:8]; /* Rs for shift */
+
+ op0_out = regs0;