- 32'b????000000??????????????1001????: begin /* Multiply */
- regsel0 = insn[15:12]; /* Rn */
- regsel1 = insn[3:0]; /* Rm */
- regsel2 = insn[11:8]; /* Rs */
- op1_res = regs1;
- new_cps = cps_in;
+ 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+ begin
+ read_0 = insn[15:12]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ read_2 = insn[11:8]; /* Rs */
+ end
+// 32'b????00001???????????????1001????, /* Multiply long */
+// read_0 = insn[11:8]; /* Rn */
+// read_1 = insn[3:0]; /* Rm */
+// read_2 = 4'b0; /* anyus */
+ 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
+ 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
+ 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ begin end /* Everything stays x'ed out. */
+ 32'b????00??????????????????????????: /* ALU */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ read_2 = insn[11:8]; /* Rs for shift */
+ end
+ 32'b????00010?00????????00001001????: /* Atomic swap */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ end
+ 32'b????000100101111111111110001????: /* Branch and exchange */
+ read_0 = insn[3:0]; /* Rn */
+ 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
+ begin
+ read_0 = insn[19:16];
+ read_1 = insn[3:0];