assign bus_rd = bus_rd_icache;
assign bus_wr = bus_wr_icache;
assign bus_ready = bus_ready_blockram;
-
+
wire [31:0] icache_rd_addr;
wire icache_rd_req;
wire icache_rd_wait;
wire execute_out_write_reg;
wire [3:0] execute_out_write_num;
wire [31:0] execute_out_write_data;
+ wire [31:0] jmppc;
+ wire jmp;
wire bubble_out_fetch;
wire bubble_out_issue;
wire [31:0] insn_out_issue;
wire [31:0] pc_out_fetch;
wire [31:0] pc_out_issue;
-
+
+ wire execute_outflush = jmp;
+ wire issue_flush = execute_outflush;
+ wire execute_flush = 1'b0;
+
BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
ICache icache(
.Nrst(1'b1 /* XXX */),
.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
- .stall(stall_cause_issue), .jmp(1'b0 /* XXX */), .jmppc(32'b0 /* XXX */),
+ .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
.bubble(bubble_out_fetch), .insn(insn_out_fetch),
.pc(pc_out_fetch));
Issue issue(
.clk(clk),
.Nrst(1'b1 /* XXX */),
- .stall(stall_cause_execute), .flush(1'b0 /* XXX */),
+ .stall(stall_cause_execute), .flush(issue_flush),
.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
Execute execute(
.clk(clk), .Nrst(1'b0),
- .stall(1'b0 /* XXX */), .flush(1'b0 /* XXX */),
+ .stall(1'b0 /* XXX */), .flush(execute_flush),
.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
.op2(decode_out_op2), .carry(decode_out_carry),
.outstall(stall_cause_execute), .outbubble(execute_out_bubble),
.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
- .write_data(execute_out_write_data));
-
+ .write_data(execute_out_write_data),
+ .jmppc(jmppc),
+ .jmp(jmp));
+
reg [31:0] clockno = 0;
always @(posedge clk)
begin