output reg write_reg = 1'bx,
output reg [3:0] write_num = 4'bxxxx,
output reg [31:0] write_data = 32'hxxxxxxxx,
output reg write_reg = 1'bx,
output reg [3:0] write_num = 4'bxxxx,
output reg [31:0] write_data = 32'hxxxxxxxx,
reg [31:0] next_outcpsr, next_outspsr;
reg next_write_reg;
reg [3:0] next_write_num;
reg [31:0] next_outcpsr, next_outspsr;
reg next_write_reg;
reg [3:0] next_write_num;
Multiplier multiplier(
.clk(clk), .Nrst(Nrst),
.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
Multiplier multiplier(
.clk(clk), .Nrst(Nrst),
.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
write_reg <= next_write_reg;
write_num <= next_write_num;
write_data <= next_write_data;
write_reg <= next_write_reg;
write_num <= next_write_num;
write_data <= next_write_data;
- outpc = pc + op0;
- if(insn[24]) begin
- next_write_reg = 1;
- next_write_num = 4'hE; /* link register */
- next_write_data = pc + 32'h4;
+ if(!inbubble && !flush) begin
+ jmppc = pc + op0 + 32'h8;
+ if(insn[24]) begin
+ next_write_reg = 1;
+ next_write_num = 4'hE; /* link register */
+ next_write_data = pc + 32'h4;
+ end
+ jmp = 1'b1;
- wire [31:0] res;
- wire flag_n, flag_z, flag_c, flag_v, setres;
+ reg [31:0] res;
+ reg flag_n, flag_z, flag_c, flag_v;
wire [32:0] sum, diff, rdiff;
wire sum_v, diff_v, rdiff_v;
wire [32:0] sum, diff, rdiff;
wire sum_v, diff_v, rdiff_v;