Fix up decode

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index 85aefbf7ac646d7ffc9e14b59af64a3731df710d..2698ecab1586deb99710a3c94bea9bce4bfa9092 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -1,155 +1,247 @@
+`include "ARM_Constants.v"
+

 module Decode(
        input clk,
 module Decode(
        input clk,

-       input [31:0] ansn,
+       input [31:0] insn,

        input [31:0] inpc,
        input [31:0] inpc,

-       input [31:0] cps_in,
+       input [31:0] incpsr,

        output reg [31:0] op0,
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg [31:0] op0,
        output reg [31:0] op1,
        output reg [31:0] op2,

-       output reg [31:0] cps_out,
+       output reg [31:0] outcpsr,

 
 

-       output [3:0] regsel0,
-       output [3:0] regsel1,
-       output [3:0] regsel2,
-       input [31:0] iregs0,
-       input [31:0] iregs1,
-       input [31:0] iregs2
+       output [3:0] read_0,
+       output [3:0] read_1,
+       output [3:0] read_2,
+       input [31:0] rdata_0,
+       input [31:0] rdata_1,
+       input [31:0] rdata_2

        );
 
        wire [31:0] regs0, regs1, regs2, rpc;
        );
 
        wire [31:0] regs0, regs1, regs2, rpc;

-       wire [31:0] op1_res, new_cps;
+       wire [31:0] op1_res, cpsr;

 
        /* shifter stuff */
        wire [31:0] shift_oper;
        wire [31:0] shift_res;
        wire shift_cflag_out;
 
 
        /* shifter stuff */
        wire [31:0] shift_oper;
        wire [31:0] shift_res;
        wire shift_cflag_out;
 

-       assign regs0 = (regsel0 == 4'b1111) ? rpc : iregs0;
-       assign regs1 = (regsel1 == 4'b1111) ? rpc : iregs1;
-       assign regs2 = iregs2; /* use regs2 for things that cannot be r15 */
+       assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
+       assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
+       assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */

 
 

-       IHATEARMSHIFT(.insn(ansn),
-                     .operand(regs1),
-                     .reg_amt(regs2),
-                     .cflag_in(cps_in[`COND_CBIT]),
-                     .res(shift_res),
-                     .cflag_out(shift_cflag));
+       IHATEARMSHIFT blowme(.insn(insn),
+                            .operand(regs1),
+                            .reg_amt(regs2),
+                            .cflag_in(incpsr[`CPSR_C]),
+                            .res(shift_res),
+                            .cflag_out(shift_cflag_out));
+       
+       always @(*)
+               casez (insn)
+               32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+//             32'b????00001???????????????1001????,   /* Multiply long */
+               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
+               32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               32'b????00010?00????????00001001????,   /* Atomic swap */
+               32'b????000100101111111111110001????,   /* Branch and exchange */
+               32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????011????????????????????1????,   /* Undefined. I hate ARM */
+               32'b????01??????????????????????????,   /* Single data transfer */
+               32'b????100?????????????????????????,   /* Block data transfer */
+               32'b????101?????????????????????????,   /* Branch */
+               32'b????110?????????????????????????,   /* Coprocessor data transfer */
+               32'b????1110???????????????????0????,   /* Coprocessor data op */
+               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1111????????????????????????:   /* SWI */
+                       rpc = inpc - 8;
+               32'b????00??????????????????????????:   /* ALU */
+                       rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+               default:                                /* X everything else out */
+                       rpc = 32'hxxxxxxxx;
+               endcase
+
+       always @(*)
+               casez (insn)
+               32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+                       read_0 = insn[15:12]; /* Rn */
+//             32'b????00001???????????????1001????,   /* Multiply long */
+//                     read_0 = insn[11:8]; /* Rn */
+               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
+               32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       read_0 = 4'hx;
+               32'b????00??????????????????????????:   /* ALU */
+                       read_0 = insn[19:16]; /* Rn */
+               32'b????00010?00????????00001001????:   /* Atomic swap */
+                       read_0 = insn[19:16]; /* Rn */
+               32'b????000100101111111111110001????:   /* Branch and exchange */
+                       read_0 = insn[3:0];   /* Rn */
+               32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
+                       read_0 = insn[19:16];
+               32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
+                       read_0 = insn[19:16];
+               32'b????011????????????????????1????:   /* Undefined. I hate ARM */
+                       read_0 = 4'hx;
+               32'b????01??????????????????????????:   /* Single data transfer */
+                       read_0 = insn[19:16]; /* Rn */
+               32'b????100?????????????????????????:   /* Block data transfer */
+                       read_0 = insn[19:16];
+               32'b????101?????????????????????????:   /* Branch */
+                       read_0 = 4'hx;
+               32'b????110?????????????????????????:   /* Coprocessor data transfer */
+                       read_0 = insn[19:16];
+               32'b????1110???????????????????0????,   /* Coprocessor data op */
+               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1111????????????????????????:   /* SWI */
+                       read_0 = 4'hx;
+               default:
+                       read_0 = 4'hx;
+               endcase
+       
+       always @(*)
+               casez (insn)
+               32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+                       read_1 = insn[3:0];   /* Rm */
+//             32'b????00001???????????????1001????:   /* Multiply long */
+//                     read_1 = insn[3:0];   /* Rm */
+               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
+               32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       read_1 = 4'hx;
+               32'b????00??????????????????????????:   /* ALU */
+                       read_1 = insn[3:0];   /* Rm */
+               32'b????00010?00????????00001001????:   /* Atomic swap */
+                       read_1 = insn[3:0];   /* Rm */
+               32'b????000100101111111111110001????:   /* Branch and exchange */
+                       read_1 = 4'hx;
+               32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
+                       read_1 = insn[3:0];
+               32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
+                       read_1 = insn[3:0];
+               32'b????011????????????????????1????:   /* Undefined. I hate ARM */
+                       read_1 = 4'hx;
+               32'b????01??????????????????????????:   /* Single data transfer */
+                       read_1 = insn[3:0];   /* Rm */
+               32'b????100?????????????????????????,   /* Block data transfer */
+               32'b????101?????????????????????????,   /* Branch */
+               32'b????110?????????????????????????,   /* Coprocessor data transfer */
+               32'b????1110???????????????????0????,   /* Coprocessor data op */
+               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1111????????????????????????:   /* SWI */
+                       read_1 = 4'hx;
+               default:
+                       read_1 = 4'hx;
+               endcase
+       
+       always @(*)
+               casez (insn)
+               32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+                       read_2 = insn[11:8];  /* Rs */
+//             32'b????00001???????????????1001????:   /* Multiply long */
+//                     read_2 = 4'b0;       /* anyus */
+               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
+               32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       read_2 = 4'hx;
+               32'b????00??????????????????????????:   /* ALU */
+                       read_2 = insn[11:8];  /* Rs for shift */
+               32'b????00010?00????????00001001????,   /* Atomic swap */
+               32'b????000100101111111111110001????,   /* Branch and exchange */
+               32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????011????????????????????1????,   /* Undefined. I hate ARM */
+               32'b????01??????????????????????????,   /* Single data transfer */
+               32'b????100?????????????????????????,   /* Block data transfer */
+               32'b????101?????????????????????????,   /* Branch */
+               32'b????110?????????????????????????,   /* Coprocessor data transfer */
+               32'b????1110???????????????????0????,   /* Coprocessor data op */
+               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1111????????????????????????:   /* SWI */
+                       read_2 = 4'hx;
+               default:
+                       read_2 = 4'hx;
+               endcase

 
        always @ (*) begin
 
        always @ (*) begin

-               casez (ansn)
+               op1_res = 32'hxxxxxxxx;
+               cpsr = 32'hxxxxxxxx;
+               casez (insn)

                32'b????000000??????????????1001????: begin /* Multiply */
                32'b????000000??????????????1001????: begin /* Multiply */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[15:12]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       regsel2 = ansn[11:8];  /* Rs */
-                       op1_res = regs1;
-                       new_cps = cps_in;
-               end
-/*
-               32'b????00001???????????????1001????: begin * Multiply long *
-                       regsel0 = ansn[11:8]; * Rn *
-                       regsel1 = ansn[3:0];  * Rm *
-                       regsel2 = 4'b0;       * anyus *

                        op1_res = regs1;
                        op1_res = regs1;

+                       cpsr = incpsr;

                end
                end

-*/
+//             32'b????00001???????????????1001????: begin /* Multiply long */
+//                     op1_res = regs1;
+//             end

                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */

-                       rpc = inpc - 8;
-                       new_cps = cps_in;
+                       cpsr = incpsr;

                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */

-                       rpc = inpc - 8;
-                       new_cps = cps_in;
+                       cpsr = incpsr;

                end
                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
                end
                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */

-                       rpc = inpc - 8;
-                       new_cps = cps_in;
+                       cpsr = incpsr;

                 end
                32'b????00??????????????????????????: begin /* ALU */
                 end
                32'b????00??????????????????????????: begin /* ALU */

-                       rpc = inpc - (ansn[25] ? 8 : (ansn[4] ? 12 : 8));
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       regsel2 = ansn[11:8];  /* Rs for shift */
-                       if(ansn[25]) begin     /* the constant case */
-                               new_cps = cps_in;
-                               op1_res = ({24'b0, ansn[7:0]} >> {ansn[11:8], 1'b0}) | ({24'b0, ansn[7:0]} << (5'b0 - {ansn[11:8], 1'b0}));
+                       if(insn[25]) begin     /* the constant case */
+                               cpsr = incpsr;
+                               op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));

                        end else begin
                        end else begin

-                               new_cps = {shift_cflag_out, cps_in[30:0]};
+                               cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};

                                op1_res = shift_res;
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */
                                op1_res = shift_res;
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       regsel2 = 4'b0;        /* anyus */

                        op1_res = regs1;
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */
                        op1_res = regs1;
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[3:0];   /* Rn */
-                       new_cps = cps_in;
+                       cpsr = incpsr;

                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       regsel1 = ansn[3:0];
-                       regsel2 = 4'b0;

                        op1_res = regs1;
                        op1_res = regs1;

-                       new_cps = cps_in;
+                       cpsr = incpsr;

                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       regsel1 = ansn[3:0];
-                       op1_res = {24'b0, ansn[11:8], ansn[3:0]};
-                       new_cps = cps_in;
+                       op1_res = {24'b0, insn[11:8], insn[3:0]};
+                       cpsr = incpsr;

                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */
                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       if(ansn[25]) begin
-                               op1_res = {20'b0, ansn[11:0]};
-                               new_cps = cps_in;
+                       if(insn[25]) begin
+                               op1_res = {20'b0, insn[11:0]};
+                               cpsr = incpsr;

                        end else begin
                                op1_res = shift_res;
                        end else begin
                                op1_res = shift_res;

-                               new_cps = shift_cflag_out;
+                               cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};

                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */
                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       op1_res = {16'b0, ansn[15:0]};
-                       new_cps = cps_in;
+                       op1_res = {16'b0, insn[15:0]};
+                       cpsr = incpsr;

                end
                32'b????101?????????????????????????: begin /* Branch */
                end
                32'b????101?????????????????????????: begin /* Branch */

-                       rpc = inpc - 8;
-                       op1_res = {6{ansn[23]}, ansn[23:0], 2'b0};
-                       new_cps = cps_in;
+                       op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
+                       cpsr = incpsr;

                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */
                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       op1_res = {24'b0, ansn[7:0]};
-                       new_cps = cps_in;
+                       op1_res = {24'b0, insn[7:0]};
+                       cpsr = incpsr;

                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */
                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */

-                       rpc = inpc - 8;
-                       new_cps = cps_in;
+                       cpsr = incpsr;

                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */

-                       rpc = inpc - 8;
-                       new_cps = cps_in;
+                       cpsr = incpsr;

                end
                32'b????1111????????????????????????: begin /* SWI */
                end
                32'b????1111????????????????????????: begin /* SWI */

-                       rpc = inpc - 8;
-                       new_cps = cps_in;
+                       cpsr = incpsr;

                end
                end

-               default:
+               default: begin end

                endcase
        end
 
                endcase
        end
 


@@ -157,7 +249,7 @@ module Decode(
                op0 <= regs0;   /* Rn - always */
                op1 <= op1_res; /* 'operand 2' - Rm */
                op2 <= regs2;   /* thirdedge - Rs */
                op0 <= regs0;   /* Rn - always */
                op1 <= op1_res; /* 'operand 2' - Rm */
                op2 <= regs2;   /* thirdedge - Rs */

-               cps_out <= new_cps;
+               outcpsr <= cpsr;

        end
 
 endmodule
        end
 
 endmodule


@@ -170,22 +262,22 @@ module IHATEARMSHIFT(
        output [31:0] res,
        output cflag_out
 );
        output [31:0] res,
        output cflag_out
 );

-       wire [1:0] shift_type;

        wire [5:0] shift_amt;
        wire elanus;
 
        wire [5:0] shift_amt;
        wire elanus;
 

-       shift_type = insn[6:5];
-       if(insn[4]) begin
-               shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
-               elanus = 1'b1;
-       end else begin
-               shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
-               elanus = 1'b0;
-       end

 
        /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
 
        /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */

-       always @ (*) begin
-               case (shift_type)
+       always @(*)
+               if(insn[4]) begin
+                       shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
+                       elanus = 1'b1;
+               end else begin
+                       shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
+                       elanus = 1'b0;
+               end
+       
+       always @(*)
+               case (insn[6:5]) /* shift type */

                `SHIFT_LSL: begin
                        {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
                end
                `SHIFT_LSL: begin
                        {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
                end


@@ -199,7 +291,7 @@ module IHATEARMSHIFT(
                        if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
                                res = {cflag_in, operand[31:1]};
                                cflag_out = operand[0];
                        if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
                                res = {cflag_in, operand[31:1]};
                                cflag_out = operand[0];

-                       end else if(!shift_amt) begin
+                       end else if(shift_amt == 6'b0) begin

                                res = operand;
                                cflag_out = cflag_in;
                        end else begin
                                res = operand;
                                cflag_out = cflag_in;
                        end else begin


@@ -207,5 +299,5 @@ module IHATEARMSHIFT(
                                cflag_out = operand[shift_amt[4:0] - 5'b1];
                        end
                end
                                cflag_out = operand[shift_amt[4:0] - 5'b1];
                        end
                end

-       end
+               endcase

 endmodule
 endmodule