+ 4'b0010: begin
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+ casez(regs)
+ 16'b???????????????1: begin
+ cur_reg = 4'h0;
+ next_regs = {regs[15:1], 1'b0};
+ end
+ 16'b??????????????10: begin
+ cur_reg = 4'h1;
+ next_regs = {regs[15:2], 2'b0};
+ end
+ 16'b?????????????100: begin
+ cur_reg = 4'h2;
+ next_regs = {regs[15:3], 3'b0};
+ end
+ 16'b????????????1000: begin
+ cur_reg = 4'h3;
+ next_regs = {regs[15:4], 4'b0};
+ end
+ 16'b???????????10000: begin
+ cur_reg = 4'h4;
+ next_regs = {regs[15:5], 5'b0};
+ end
+ 16'b??????????100000: begin
+ cur_reg = 4'h5;
+ next_regs = {regs[15:6], 6'b0};
+ end
+ 16'b?????????1000000: begin
+ cur_reg = 4'h6;
+ next_regs = {regs[15:7], 7'b0};
+ end
+ 16'b????????10000000: begin
+ cur_reg = 4'h7;
+ next_regs = {regs[15:8], 8'b0};
+ end
+ 16'b???????100000000: begin
+ cur_reg = 4'h8;
+ next_regs = {regs[15:9], 9'b0};
+ end
+ 16'b??????1000000000: begin
+ cur_reg = 4'h9;
+ next_regs = {regs[15:10], 10'b0};
+ end
+ 16'b?????10000000000: begin
+ cur_reg = 4'hA;
+ next_regs = {regs[15:11], 11'b0};
+ end
+ 16'b????100000000000: begin
+ cur_reg = 4'hB;
+ next_regs = {regs[15:12], 12'b0};
+ end
+ 16'b???1000000000000: begin
+ cur_reg = 4'hC;
+ next_regs = {regs[15:13], 13'b0};
+ end
+ 16'b??10000000000000: begin
+ cur_reg = 4'hD;
+ next_regs = {regs[15:14], 14'b0};
+ end
+ 16'b?100000000000000: begin
+ cur_reg = 4'hE;
+ next_regs = {regs[15], 15'b0};
+ end
+ 16'b1000000000000000: begin
+ cur_reg = 4'hF;
+ next_regs = 16'b0;
+ end
+ default: begin
+ cur_reg = 4'hx;
+ next_regs = 16'b0;
+ end
+ endcase
+ cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
+ if(cur_reg == 4'hF && insn[22]) begin
+ next_outcpsr = spsr;
+ next_outcpsrup = 1;
+ end
+
+ offset = prev_offset + 6'h4;
+ offset_sel = insn[24] ? offset : prev_offset;
+ raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+ if(insn[20]) begin
+ next_write_reg = !rw_wait;
+ next_write_num = cur_reg;
+ next_write_data = rd_data;
+ end
+ if (rw_wait) begin
+ next_regs = regs;
+ cur_reg = prev_reg; /* whoops, do this one again */
+ end
+
+ st_read = cur_reg;
+ wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
+ busaddr = raddr;
+
+ $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
+
+ outstall = 1'b1;
+
+ if(next_regs == 16'b0) begin
+ next_lsm_state = 4'b0100;
+ end