+
+ /* Coprocessor input. */
+ always @(*)
+ begin
+ cp_req = 0;
+ cp_rnw = 1'bx;
+ cp_write = 32'hxxxxxxxx;
+ casez (insn_3a)
+ `DECODE_CDP: if(!bubble_3a) begin
+ cp_req = 1;
+ end
+ `DECODE_MRCMCR: if(!bubble_3a) begin
+ cp_req = 1;
+ cp_rnw = insn_3a[20] /* L */;
+ if (insn_3a[20] == 0 /* store to coprocessor */)
+ cp_write = op0_3a;
+ end
+ endcase
+ end
+
+ /* Register output logic. */
+ always @(*)
+ begin
+ next_write_reg = write_reg_3a;
+ next_write_num = write_num_3a;
+ next_write_data = write_data_3a;
+ next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr_3a;
+ next_outcpsrup = cpsrup_3a;
+
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if (!bubble_3a) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(swp_state)
+ `SWP_READING:
+ next_write_reg = 1'b0;
+ `SWP_WRITING: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn_3a[15:12];
+ next_write_data = insn_3a[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
+ end
+ default: begin end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin
+ next_write_reg = write_reg_3a; /* XXX workaround for ISE 10.1 bug */
+ next_write_num = write_num_3a;
+ next_write_data = write_data_3a;
+ next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr_3a;
+ next_outcpsrup = cpsrup_3a;
+ end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(lsrh_state)
+ `LSRH_MEMIO: begin
+ next_write_num = insn_3a[15:12];
+ next_write_data = lsrh_rddata;
+ if(insn_3a[20]) begin
+ next_write_reg = 1'b1;
+ end
+ end
+ `LSRH_BASEWB: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn_3a[19:16];
+ next_write_data = addr;
+ end
+ `LSRH_WBFLUSH:
+ next_write_reg = 1'b0;
+ default: begin end
+ endcase
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!bubble_3a) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(lsr_state)
+ `LSR_MEMIO: begin
+ next_write_reg = insn_3a[20] /* L */;
+ next_write_num = insn_3a[15:12];
+ if(insn_3a[20] /* L */) begin
+ next_write_data = insn_3a[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
+ end
+ end
+ `LSR_STRB_WR:
+ next_write_reg = 1'b0;
+ `LSR_BASEWB: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn_3a[19:16];
+ next_write_data = addr;
+ end
+ `LSR_WBFLUSH:
+ next_write_reg = 1'b0;
+ default: begin end
+ endcase
+ end
+ `DECODE_LDMSTM: if(!bubble_3a) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(lsm_state)
+ `LSM_SETUP:
+ next_write_reg = 1'b0;
+ `LSM_MEMIO: begin
+ if(insn_3a[20] /* L */) begin
+ next_write_reg = !dc__rw_wait_3a;
+ next_write_num = cur_reg;
+ next_write_data = dc__rd_data_3a;
+ end else
+ next_write_reg = 1'b0;
+ end
+ `LSM_BASEWB: begin
+ next_write_reg = insn_3a[21] /* writeback */;
+ next_write_num = insn_3a[19:16];
+ next_write_data = insn_3a[23] ? op0_3a + {26'b0, prev_offset} : op0_3a - {26'b0, prev_offset};
+ if(cur_reg == 4'hF && insn_3a[22]) begin
+ next_outcpsr = spsr_3a;
+ next_outcpsrup = 1;
+ end
+ end
+ `LSM_WBFLUSH:
+ next_write_reg = 1'b0;
+ default: begin end
+ endcase
+ end
+ `DECODE_MRCMCR: if(!bubble_3a) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ next_outcpsr = 32'hxxxxxxxx;
+ next_outcpsrup = 1'bx;
+ if (insn_3a[20] == 1 /* load from coprocessor */)
+ if (insn_3a[15:12] != 4'hF /* Fuck you ARM */) begin
+ next_write_reg = 1'b1;
+ next_write_num = insn_3a[15:12];
+ next_write_data = cp_read;
+ end else begin
+ next_outcpsr = {cp_read[31:28], cpsr_3a[27:0]};
+ next_outcpsrup = 1;
+ end
+ end
+ endcase
+ end
+
+ /* Bus/address control logic. */
+ always @(*)
+ begin
+ dc__rd_req_3a = 1'b0;
+ dc__wr_req_3a = 1'b0;
+ offset = prev_offset;
+ addr = prevaddr;
+ raddr = 32'hxxxxxxxx;
+ dc__addr_3a = 32'hxxxxxxxx;
+ dc__data_size_3a = 3'bxxx;
+
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if(!bubble_3a) begin
+ dc__addr_3a = {op0_3a[31:2], 2'b0};
+ dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
+ case(swp_state)
+ `SWP_READING:
+ dc__rd_req_3a = 1'b1;
+ `SWP_WRITING:
+ dc__wr_req_3a = 1'b1;
+ default: begin end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin
+ dc__rd_req_3a = 1'b0; /* XXX workaround for Xilinx bug */
+ dc__wr_req_3a = 1'b0;
+ offset = prev_offset;
+ addr = prevaddr;
+ end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
+ addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
+ raddr = insn_3a[24] ? op0_3a : addr; /* pre/post increment */
+ dc__addr_3a = raddr;
+ /* rotate to correct position */
+ case(insn_3a[6:5])
+ 2'b01: /* unsigned half */
+ dc__data_size_3a = 3'b010;
+ 2'b10: /* signed byte */
+ dc__data_size_3a = 3'b001;
+ 2'b11: /* signed half */
+ dc__data_size_3a = 3'b010;
+ default: begin
+ dc__data_size_3a = 3'bxxx;
+ end
+ endcase
+
+ case(lsrh_state)
+ `LSRH_MEMIO: begin
+ dc__rd_req_3a = insn_3a[20];
+ dc__wr_req_3a = ~insn_3a[20];
+ end
+ `LSRH_BASEWB: begin end
+ `LSRH_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!bubble_3a) begin
+ addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
+ raddr = insn_3a[24] ? addr : op0_3a; /* pre/post increment */
+ dc__addr_3a = raddr;
+ dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
+ case (lsr_state)
+ `LSR_MEMIO: begin
+ dc__rd_req_3a = insn_3a[20] /* L */ || insn_3a[22] /* B */;
+ dc__wr_req_3a = !insn_3a[20] /* L */ && !insn_3a[22]/* B */;
+ end
+ `LSR_STRB_WR:
+ dc__wr_req_3a = 1;
+ `LSR_BASEWB: begin end
+ `LSR_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDMSTM: if (!bubble_3a) begin
+ dc__data_size_3a = 3'b100;
+ case (lsm_state)
+ `LSM_SETUP:
+ offset = 6'b0;
+ `LSM_MEMIO: begin
+ dc__rd_req_3a = insn_3a[20];
+ dc__wr_req_3a = ~insn_3a[20];
+ offset = prev_offset + 6'h4;
+ offset_sel = insn_3a[24] ? offset : prev_offset;
+ raddr = insn_3a[23] ? op0_3a + {26'b0, offset_sel} : op0_3a - {26'b0, offset_sel};
+ dc__addr_3a = raddr;
+ end
+ `LSM_BASEWB: begin end
+ `LSM_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* Bus data control logic. */
+ always @(*)
+ begin
+ dc__wr_data_3a = 32'hxxxxxxxx;
+
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if(!bubble_3a)
+ if (swp_state == `SWP_WRITING)
+ dc__wr_data_3a = insn_3a[22] ? {4{op1_3a[7:0]}} : op1_3a;
+ `DECODE_ALU_MULT: begin end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a)
+ case(insn_3a[6:5])
+ 2'b01: /* unsigned half */
+ dc__wr_data_3a = {2{op2_3a[15:0]}}; /* XXX need to store halfword */
+ 2'b10: /* signed byte */
+ dc__wr_data_3a = {4{op2_3a[7:0]}};
+ 2'b11: /* signed half */
+ dc__wr_data_3a = {2{op2_3a[15:0]}};
+ default: begin end
+ endcase
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!bubble_3a) begin
+ dc__wr_data_3a = insn_3a[22] ? {24'h0, {op2_3a[7:0]}} : op2_3a;
+ if (lsr_state == `LSR_STRB_WR)
+ case (dc__addr_3a[1:0])
+ 2'b00: dc__wr_data_3a = {rd_data_latch[31:8], op2_3a[7:0]};
+ 2'b01: dc__wr_data_3a = {rd_data_latch[31:16], op2_3a[7:0], rd_data_latch[7:0]};
+ 2'b10: dc__wr_data_3a = {rd_data_latch[31:24], op2_3a[7:0], rd_data_latch[15:0]};
+ 2'b11: dc__wr_data_3a = {op2_3a[7:0], rd_data_latch[23:0]};
+ endcase
+ end
+ `DECODE_LDMSTM: if (!bubble_3a)
+ if (lsm_state == `LSM_MEMIO)
+ dc__wr_data_3a = (cur_reg == 4'hF) ? (pc_3a + 12) : rf__rdata_3_3a;
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* LDM/STM register control logic. */