-
- always @(*)
- casez (insn)
- 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
- read_0 = insn[15:12]; /* Rn */
-// 32'b????00001???????????????1001????, /* Multiply long */
-// read_0 = insn[11:8]; /* Rn */
- 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
- 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
- 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
- read_0 = 4'hx;
- 32'b????00??????????????????????????: /* ALU */
- read_0 = insn[19:16]; /* Rn */
- 32'b????00010?00????????00001001????: /* Atomic swap */
- read_0 = insn[19:16]; /* Rn */
- 32'b????000100101111111111110001????: /* Branch and exchange */
- read_0 = insn[3:0]; /* Rn */
- 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
- read_0 = insn[19:16];
- 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */
- read_0 = insn[19:16];
- 32'b????011????????????????????1????: /* Undefined. I hate ARM */
- read_0 = 4'hx;
- 32'b????01??????????????????????????: /* Single data transfer */
- read_0 = insn[19:16]; /* Rn */
- 32'b????100?????????????????????????: /* Block data transfer */
- read_0 = insn[19:16];
- 32'b????101?????????????????????????: /* Branch */
- read_0 = 4'hx;
- 32'b????110?????????????????????????: /* Coprocessor data transfer */
- read_0 = insn[19:16];
- 32'b????1110???????????????????0????, /* Coprocessor data op */
- 32'b????1110???????????????????1????, /* Coprocessor register transfer */
- 32'b????1111????????????????????????: /* SWI */
- read_0 = 4'hx;
- default:
- read_0 = 4'hx;
- endcase