- IHATEARMSHIFT blowme(.insn(insn),
- .operand(regs1),
- .reg_amt(regs2),
- .cflag_in(incpsr[`CPSR_C]),
- .res(shift_res),
- .cflag_out(shift_cflag_out));
-
- always @(*)
- casez (insn)
- 32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
-// 32'b????00001???????????????1001????, /* Multiply long */
- 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
- 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
- 32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
- 32'b????00010?00????????00001001????, /* Atomic swap */
- 32'b????000100101111111111110001????, /* Branch and exchange */
- 32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
- 32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
- 32'b????011????????????????????1????, /* Undefined. I hate ARM */
- 32'b????01??????????????????????????, /* Single data transfer */
- 32'b????100?????????????????????????, /* Block data transfer */
- 32'b????101?????????????????????????, /* Branch */
- 32'b????110?????????????????????????, /* Coprocessor data transfer */
- 32'b????1110???????????????????0????, /* Coprocessor data op */
- 32'b????1110???????????????????1????, /* Coprocessor register transfer */
- 32'b????1111????????????????????????: /* SWI */
- rpc = inpc - 8;
- 32'b????00??????????????????????????: /* ALU */
- rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
- default: /* X everything else out */
- rpc = 32'hxxxxxxxx;
- endcase
+ IREALLYHATEARMSHIFT shift(.insn(insn),
+ .operand(regs1),
+ .reg_amt(regs2),
+ .cflag_in(incpsr[`CPSR_C]),
+ .res(shift_res),
+ .cflag_out(shift_cflag_out));
+
+ SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
+ .amt(insn[11:8]),
+ .res(rotate_res));