Memory: Add CDP and MRC/MCR.

[firearm.git] / Memory.v

diff --git a/Memory.v b/Memory.v
index e04a8049861508b8f1b3f0c42941df1e739dddd5..2885addccb1334164c640ba6b44c623cbf816f3b 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -16,6 +16,14 @@ module Memory(
        output reg [3:0] st_read,
        input [31:0] st_data,
        
        output reg [3:0] st_read,
        input [31:0] st_data,
        

+       /* Coprocessor interface */
+       output reg cp_req,
+       input cp_ack,
+       input cp_busy,
+       output cp_rnw,  /* 1 = read from CP, 0 = write to CP */
+       input [31:0] cp_read,
+       output reg [31:0] cp_write,
+       

        /* stage inputs */
        input inbubble,
        input [31:0] pc,
        /* stage inputs */
        input inbubble,
        input [31:0] pc,


@@ -23,6 +31,8 @@ module Memory(
        input [31:0] op0,
        input [31:0] op1,
        input [31:0] op2,
        input [31:0] op0,
        input [31:0] op1,
        input [31:0] op2,

+       input [31:0] spsr,
+       input [31:0] cpsr,

        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,
        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,


@@ -34,10 +44,12 @@ module Memory(
        output reg [31:0] outinsn,
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] outinsn,
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,

-       output reg [31:0] out_write_data = 32'hxxxxxxxx
+       output reg [31:0] out_write_data = 32'hxxxxxxxx,
+       output reg [31:0] out_spsr = 32'hxxxxxxxx,
+       output reg [31:0] out_cpsr = 32'hxxxxxxxx

        );
 
        );
 

-       reg [31:0] addr, raddr, prev_raddr, next_regdata;
+       reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;

        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback, next_notdone, next_inc_next;
        reg [31:0] align_s1, align_s2, align_rddata;
        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback, next_notdone, next_inc_next;
        reg [31:0] align_s1, align_s2, align_rddata;


@@ -69,6 +81,8 @@ module Memory(
                started <= next_started;
                prev_offset <= offset;
                prev_raddr <= raddr;
                started <= next_started;
                prev_offset <= offset;
                prev_raddr <= raddr;

+               out_cpsr <= next_outcpsr;
+               out_spsr <= spsr;

        end
 
        always @(*)
        end
 
        always @(*)


@@ -89,7 +103,11 @@ module Memory(
                outstall = 1'b0;
                next_regs = 16'b0;
                next_started = started;
                outstall = 1'b0;
                next_regs = 16'b0;
                next_started = started;

+               cp_req = 1'b0;
+               cp_rnw = 1'bx;
+               cp_write = 32'hxxxxxxxx;

                offset = prev_offset;
                offset = prev_offset;

+               next_outcpsr = started ? out_cpsr : cpsr;

 
                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end
 
                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end


@@ -223,6 +241,9 @@ module Memory(
                                end
                                endcase
                                cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
                                end
                                endcase
                                cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;

+                               if(cur_reg == 4'hF && insn[22]) begin
+                                       next_outcpsr = spsr;
+                               end

                                offset = prev_offset + 6'h4;
                                offset_sel = insn[24] ? offset : prev_offset;
                                raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
                                offset = prev_offset + 6'h4;
                                offset_sel = insn[24] ? offset : prev_offset;
                                raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};


@@ -237,10 +258,42 @@ module Memory(
                                wr_data = st_data;
 
                                next_inc_next = next_regs == 16'b0;
                                wr_data = st_data;
 
                                next_inc_next = next_regs == 16'b0;

-                               next_notdone = ~next_inc_next | (rw_wait & insn[20] & insn[21]);
+                               next_notdone = ~next_inc_next | rw_wait;

                                busaddr = {raddr[31:2], 2'b0};
                        end
                end
                                busaddr = {raddr[31:2], 2'b0};
                        end
                end

+               `DECODE_LDCSTC: begin
+                       $display("WARNING: Unimplemented LDCSTC");
+               end
+               `DECODE_CDP: begin
+                       cp_req = 1;
+                       if (cp_busy) begin
+                               outstall = 1;
+                               next_outbubble = 1;
+                       end
+                       if (!cp_ack) begin
+                               /* XXX undefined instruction trap */
+                               $display("WARNING: Possible CDP undefined instruction");
+                       end
+               end
+               `DECODE_MRCMCR: begin
+                       cp_req = 1;
+                       cp_rnw = insn[20] /* L */;
+                       if (insn[20] == 0 /* store to coprocessor */)
+                               cp_write = op0;
+                       else begin
+                               next_write_reg = 1'b1;
+                               next_write_num = insn[15:12];
+                               next_write_data = cp_read;
+                       end
+                       if (cp_busy) begin
+                               outstall = 1;
+                               next_outbubble = 1;
+                       end
+                       if (!cp_ack) begin
+                               $display("WARNING: Possible MRCMCR undefined instruction");
+                       end
+               end

                default: begin end
                endcase
        end
                default: begin end
                endcase
        end