`else
, output wire [8:0] sys_odata,
input [8:0] sys_idata,
- output wire sys_tookdata
+ output wire sys_tookdata,
+
+ output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+ inout wire [15:0] cr_DQ,
+ output wire [22:0] cr_A,
+ output wire st_nCE
`endif
);
wire bus_rd_dcache;
wire bus_wr_dcache;
- wire [31:0] bus_rdata_blockram;
- wire bus_ready_blockram;
+ wire [31:0] bus_rdata_blockram, bus_rdata_cellularram;
+ wire bus_ready_blockram, bus_ready_cellularram;
assign bus_addr = bus_addr_icache | bus_addr_dcache;
- assign bus_rdata = bus_rdata_blockram;
+ assign bus_rdata = bus_rdata_blockram | bus_rdata_cellularram;
assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
assign bus_rd = bus_rd_icache | bus_rd_dcache;
assign bus_wr = bus_wr_icache | bus_wr_dcache;
- assign bus_ready = bus_ready_blockram;
+ assign bus_ready = bus_ready_blockram | bus_ready_cellularram;
wire [31:0] icache_rd_addr;
wire icache_rd_req;
wire [31:0] cpsr_2a; // From decode of Decode.v
wire [31:0] cpsr_3a; // From execute of Execute.v
wire cpsrup_3a; // From execute of Execute.v
+ wire [31:0] dc__addr_3a; // From memory of Memory.v
wire [2:0] dc__data_size_3a; // From memory of Memory.v
+ wire [31:0] dc__rd_data_3a; // From dcache of DCache.v
+ wire dc__rd_req_3a; // From memory of Memory.v
+ wire dc__rw_wait_3a; // From dcache of DCache.v
+ wire [31:0] dc__wr_data_3a; // From memory of Memory.v
+ wire dc__wr_req_3a; // From memory of Memory.v
wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
wire [31:0] ic__rd_data_1a; // From icache of ICache.v
wire ic__rd_req_0a; // From fetch of Fetch.v
.bus_wr(bus_wr_icache),
.bus_ready(bus_ready),
); */
- ICache icache(/*AUTOINST*/
+ ICache icache(
+ /*AUTOINST*/
// Outputs
.ic__rd_wait_0a (ic__rd_wait_0a),
.ic__rd_data_1a (ic__rd_data_1a[31:0]),
.bus_rdata (bus_rdata), // Templated
.bus_ready (bus_ready)); // Templated
- DCache dcache(
+ /* DCache AUTO_TEMPLATE (
.clk(clk),
- .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
- .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
- .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
- .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
- .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
- .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
+ .bus_req(bus_req_dcache),
+ .bus_ack(bus_ack_dcache),
+ .bus_addr(bus_addr_dcache),
+ .bus_rdata(bus_rdata),
+ .bus_wdata(bus_wdata_dcache),
+ .bus_rd(bus_rd_dcache),
+ .bus_wr(bus_wr_dcache),
+ .bus_ready(bus_ready),
+ );
+ */
+ DCache dcache(
+ /*AUTOINST*/
+ // Outputs
+ .dc__rw_wait_3a (dc__rw_wait_3a),
+ .dc__rd_data_3a (dc__rd_data_3a[31:0]),
+ .bus_req (bus_req_dcache), // Templated
+ .bus_addr (bus_addr_dcache), // Templated
+ .bus_wdata (bus_wdata_dcache), // Templated
+ .bus_rd (bus_rd_dcache), // Templated
+ .bus_wr (bus_wr_dcache), // Templated
+ // Inputs
+ .clk (clk), // Templated
+ .dc__addr_3a (dc__addr_3a[31:0]),
+ .dc__rd_req_3a (dc__rd_req_3a),
+ .dc__wr_req_3a (dc__wr_req_3a),
+ .dc__wr_data_3a (dc__wr_data_3a[31:0]),
+ .bus_ack (bus_ack_dcache), // Templated
+ .bus_rdata (bus_rdata), // Templated
+ .bus_ready (bus_ready)); // Templated
`ifdef verilator
BigBlockRAM
.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
.bus_ready(bus_ready_blockram));
+`ifdef verilator
+ assign bus_rdata_cellularram = 32'h00000000;
+ assign bus_ready_cellularram = 0;
+`else
+ /* CellularRAM AUTO_TEMPLATE (
+ .bus_rdata(bus_rdata_cellularram),
+ .bus_ready(bus_ready_cellularram),
+ );
+ */
+ CellularRAM cellularram(
+ /*AUTOINST*/
+ // Outputs
+ .bus_rdata (bus_rdata_cellularram), // Templated
+ .bus_ready (bus_ready_cellularram), // Templated
+ .cr_nADV (cr_nADV),
+ .cr_nCE (cr_nCE),
+ .cr_nOE (cr_nOE),
+ .cr_nWE (cr_nWE),
+ .cr_CRE (cr_CRE),
+ .cr_nLB (cr_nLB),
+ .cr_nUB (cr_nUB),
+ .cr_CLK (cr_CLK),
+ .cr_A (cr_A[22:0]),
+ .st_nCE (st_nCE),
+ // Inouts
+ .cr_DQ (cr_DQ[15:0]),
+ // Inputs
+ .clk (clk),
+ .bus_addr (bus_addr[31:0]),
+ .bus_wdata (bus_wdata[31:0]),
+ .bus_rd (bus_rd),
+ .bus_wr (bus_wr));
+`endif
+
/* Fetch AUTO_TEMPLATE (
.jmp_0a(jmp),
.jmppc_0a(jmppc),
.carry_2a (carry_2a));
assign execute_out_backflush = jmp;
- assign cp_insn = insn_out_execute;
+ assign cp_insn = insn_3a;
/* stall? */
/* Memory AUTO_TEMPLATE (
.flush(writeback_out_backflush),
- .dc__addr_3a(dcache_addr),
- .dc__rd_req_3a(dcache_rd_req),
- .dc__wr_req_3a(dcache_wr_req),
- .dc__rw_wait_3a(dcache_rw_wait),
- .dc__wr_data_3a(dcache_wr_data),
- .dc__rd_data_3a(dcache_rd_data),
.outstall(stall_cause_memory),
.outbubble(bubble_out_memory),
.outpc(pc_out_memory),
Memory memory(
/*AUTOINST*/
// Outputs
- .dc__addr_3a (dcache_addr), // Templated
- .dc__rd_req_3a (dcache_rd_req), // Templated
- .dc__wr_req_3a (dcache_wr_req), // Templated
- .dc__wr_data_3a (dcache_wr_data), // Templated
+ .dc__addr_3a (dc__addr_3a[31:0]),
+ .dc__rd_req_3a (dc__rd_req_3a),
+ .dc__wr_req_3a (dc__wr_req_3a),
+ .dc__wr_data_3a (dc__wr_data_3a[31:0]),
.dc__data_size_3a (dc__data_size_3a[2:0]),
.rf__read_3_3a (rf__read_3_3a[3:0]),
.cp_req (cp_req), // Templated
.clk (clk),
.Nrst (Nrst),
.flush (writeback_out_backflush), // Templated
- .dc__rw_wait_3a (dcache_rw_wait), // Templated
- .dc__rd_data_3a (dcache_rd_data), // Templated
+ .dc__rw_wait_3a (dc__rw_wait_3a),
+ .dc__rd_data_3a (dc__rd_data_3a[31:0]),
.rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
.cp_ack (cp_ack), // Templated
.cp_busy (cp_busy), // Templated
$display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
$display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
$display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
- $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
+ $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_3a, insn_3a, pc_3a, write_reg_3a, write_data_3a, write_num_3a, jmp_out_execute, jmppc_out_execute);
$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
$display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
end
git.joshuawise.com / firearm.git / blobdiff