Add SPSR logic to Execute.

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index ea6cd60d3ef74e3e8cb02d35c9afdf7763f59ecb..7c7f35738011455631b86f9413e028e221ccda53 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -9,6 +9,7 @@ module Execute(
        input [31:0] pc,
        input [31:0] insn,
        input [31:0] cpsr,
+       input [31:0] spsr,
        input [31:0] op0,
        input [31:0] op1,
        input [31:0] op2,
@@ -17,6 +18,7 @@ module Execute(
        output reg outstall = 0,
        output reg outbubble = 1,
        output reg [31:0] outcpsr = 0,
+       output reg [31:0] outspsr = 0,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx
@@ -34,7 +36,7 @@ module Execute(
        wire alu_setres;
        
        reg next_outbubble;
-       reg [31:0] next_outcpsr;
+       reg [31:0] next_outcpsr, next_outspsr;
        reg next_write_reg;
        reg [3:0] next_write_num;
        reg [31:0] next_write_data;
@@ -56,6 +58,7 @@ module Execute(
                begin
                        outbubble <= next_outbubble;
                        outcpsr <= next_outcpsr;
+                       outspsr <= next_outspsr;
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
@@ -71,6 +74,7 @@ module Execute(
                outstall = stall;
                next_outbubble = inbubble;
                next_outcpsr = cpsr;
+               next_outspsr = spsr;
                next_write_reg = 0;
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;
@@ -104,9 +108,29 @@ module Execute(
                        next_write_data = mult_result;
                end
 //             `DECODE_ALU_MUL_LONG,   /* Multiply long */
-               `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
+               `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
+               begin
+                       next_write_reg = 1;
+                       next_write_num = insn[15:12];
+                       if (insn[22] /* Ps */)
+                               next_write_data = spsr;
+                       else
+                               next_write_data = cpsr;
+               end
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
-               `DECODE_ALU_MSR_FLAGS,  /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
+                       begin
+                               if (insn[22] /* Ps */)
+                                       next_outspsr = {op0[31:29], spsr[28:0]};
+                               else
+                                       next_outcpsr = {op0[31:29], cpsr[28:0]};
+                       end else begin
+                               if (insn[22] /* Ps */)
+                                       next_outspsr = op0;
+                               else
+                                       next_outcpsr = op0;
+                       end
                `DECODE_ALU_SWP,        /* Atomic swap */
                `DECODE_ALU_BX,         /* Branch */
                `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
@@ -117,7 +141,7 @@ module Execute(
                        alu_in0 = op0;
                        alu_in1 = op1;
                        alu_op = insn[24:21];
-                       alu_setflags = insn[20] /* I */;
+                       alu_setflags = insn[20] /* S */;
                        
                        if (alu_setres) begin
                                next_write_reg = 1;
@@ -125,7 +149,7 @@ module Execute(
                                next_write_data = alu_result;
                        end
                        
-                       next_outcpsr = alu_outcpsr;
+                       next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                `DECODE_LDRSTR,         /* Single data transfer */
@@ -179,7 +203,6 @@ module Multiplier(
        end
 endmodule
 
-/* XXX is the interface correct? */
 module ALU(
        input clk,
        input Nrst,     /* XXX not used yet */
@@ -198,12 +221,15 @@ module ALU(
        wire [31:0] res;
        wire flag_n, flag_z, flag_c, flag_v, setres;
        wire [32:0] sum, diff, rdiff;
+       wire sum_v, diff_v, rdiff_v;
 
        assign sum = {1'b0, in0} + {1'b0, in1};
        assign diff = {1'b0, in0} - {1'b0, in1};
        assign rdiff = {1'b0, in1} + {1'b0, in0};
+       assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
+       assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
+       assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
 
-       /* TODO XXX flag_v not set correctly */
        always @(*) begin
                res = 32'hxxxxxxxx;
                setres = 1'bx;
@@ -222,26 +248,32 @@ module ALU(
                end
                `ALU_SUB: begin
                        {flag_c, result} = diff;
+                       flag_v = diff_v;
                        setres = 1'b1;
                end
                `ALU_RSB: begin
                        {flag_c, result} = rdiff;
+                       flag_v = rdiff_v;
                        setres = 1'b1;
                end
                `ALU_ADD: begin
                        {flag_c, result} = sum;
+                       flag_v = sum_v;
                        setres = 1'b1;
                end
                `ALU_ADC: begin
                        {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
+                       flag_v = sum_v | (~sum[31] & result[31]);
                        setres = 1'b1;
                end
                `ALU_SBC: begin
                        {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
+                       flag_v = diff_v | (diff[31] & ~result[31]);
                        setres = 1'b1;
                end
                `ALU_RSC: begin
                        {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
+                       flag_v = rdiff_v | (rdiff[31] & ~result[31]);
                        setres = 1'b1;
                end
                `ALU_TST: begin
@@ -256,10 +288,12 @@ module ALU(
                end
                `ALU_CMP: begin
                        {flag_c, result} = diff;
+                       flag_v = diff_v;
                        setres = 1'b0;
                end
                `ALU_CMN: begin
                        {flag_c, result} = sum;
+                       flag_v = sum_v;
                        setres = 1'b0;
                end
                `ALU_ORR: begin