Add the DCache.

[firearm.git] / system.v

diff --git a/system.v b/system.v
index 8ab3e23cb6370b8cac6853d58d21610b90410b91..4601ae77665ccd8f89668b9c6a5901bd1a6e3252 100644 (file)
--- a/system.v
+++ b/system.v
@@ -54,6 +54,8 @@ module System(input clk);
        wire [31:0] pc_out_fetch;
        wire [31:0] pc_out_issue;
 
+       wire execute_out_backflush;
+
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
        ICache icache(
@@ -84,7 +86,7 @@ module System(input clk);
        Issue issue(
                .clk(clk),
                .Nrst(1'b1 /* XXX */),
-               .stall(stall_cause_execute), .flush(1'b0 /* XXX */),
+               .stall(stall_cause_execute), .flush(execute_out_backflush),
                .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
                .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
                .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
@@ -106,7 +108,7 @@ module System(input clk);
        
        Execute execute(
                .clk(clk), .Nrst(1'b0),
-               .stall(1'b0 /* XXX */), .flush(1'b0 /* XXX */),
+               .stall(1'b0 /* XXX */), .flush(1'b0),
                .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
                .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
                .op2(decode_out_op2), .carry(decode_out_carry),
@@ -115,6 +117,7 @@ module System(input clk);
                .write_data(execute_out_write_data),
                .jmppc(jmppc),
                .jmp(jmp));
+       assign execute_out_backflush = jmp;
 
        reg [31:0] clockno = 0;
        always @(posedge clk)