Console: Put the core in its own clock domain.
[firearm.git] / Fetch.v
diff --git a/Fetch.v b/Fetch.v
index 834a0da..3f28453 100644 (file)
--- a/Fetch.v
+++ b/Fetch.v
@@ -16,45 +16,39 @@ module Fetch(
        
        reg qjmp = 0;   /* A jump has been queued up while we were waiting. */
        reg [31:0] qjmppc;
-       always @(posedge clk)
-               if (rd_wait && jmp && !qjmp)
+       always @(posedge clk or negedge Nrst)
+               if (!Nrst)
+                       qjmp <= 0;
+               else if ((rd_wait || stall) && jmp)
                        {qjmp,qjmppc} <= {jmp, jmppc};
-               else if (!rd_wait && qjmp)      /* It has already been intoed. */
+               else if (!rd_wait && !stall && qjmp)    /* It has already been intoed. */
                        {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
        
        reg [31:0] reqpc;
-       always @(*)
-               if (stall)
-                       reqpc = pc;
-               else if (qjmp)
-                       reqpc = qjmppc;
-               else if (jmp)
-                       reqpc = jmppc;
-               else
-                       reqpc = pc + 4;
        
+       /* Output latch logic */
        assign rd_addr = reqpc;
        assign rd_req = 1;
-       
-       always @(negedge Nrst)
-       begin
-               pc <= 32'hFFFFFFFC;
-               qjmp <= 0;
-               bubble <= 1;
-       end
-       
-       always @(posedge clk)
-       begin
+       always @(posedge clk or negedge Nrst)
                if (!Nrst) begin
-                       pc <= 32'hFFFFFFFC;
-                       qjmp <= 0;
                        bubble <= 1;
-               end else if (!stall)
-               begin
-                       bubble <= rd_wait;
+                       insn <= 0;
+                       pc <= 32'h00000000;
+               end else if (!stall) begin
+                       bubble <= (jmp || qjmp || rd_wait);
                        insn <= rd_data;
-                       if (!rd_wait)
-                               pc <= reqpc;
+                       pc <= reqpc;
+               end
+       
+       always @(posedge clk or negedge Nrst)
+               if (!Nrst)
+                       reqpc <= 0;
+               else if (!stall && !rd_wait) begin
+                       if (qjmp)
+                               reqpc <= qjmppc;
+                       else if (jmp)
+                               reqpc <= jmppc;
+                       else
+                               reqpc <= reqpc + 4;
                end
-       end
 endmodule
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