- input [31:0] incpsr,
- input [31:0] inspsr,
- output reg [31:0] op0,
- output reg [31:0] op1,
- output reg [31:0] op2,
- output reg carry,
- output reg [31:0] outcpsr,
- output reg [31:0] outspsr,
+ input [31:0] cpsr_1a,
+ input [31:0] spsr_1a,
+ output reg [31:0] op0_2a,
+ output reg [31:0] op1_2a,
+ output reg [31:0] op2_2a,
+ output reg carry_2a,
+ output reg [31:0] cpsr_2a,
+ output reg [31:0] spsr_2a,