Add wires for ALU.

[firearm.git] / Issue.v

diff --git a/Issue.v b/Issue.v
index 6b25d3752a044e54e56f77c3c83d7acfc2b0e810..fcc2c0c8d6d64b60a758bd3bace800611b54cf61 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -5,17 +5,17 @@ module Issue(
        input Nrst,     /* XXX not used yet */
        
        input stall,    /* pipeline control */
-       input flush,
+       input flush,    /* XXX not used yet */
        
        input inbubble, /* stage inputs */
        input [31:0] insn,
        input [31:0] inpc,
        input [31:0] cpsr,
        
-       output reg outstall,    /* stage outputs */
-       output reg outbubble,
-       output reg [31:0] outpc,
-       output reg [31:0] outinsn
+       output reg outstall = 0,        /* stage outputs */
+       output reg outbubble = 1,
+       output reg [31:0] outpc = 0,
+       output reg [31:0] outinsn = 0
        /* XXX other? */
        );
        
@@ -276,19 +276,25 @@ module Issue(
        begin
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
+               
+               outstall = waiting && !inbubble;        /* Happens in an always @*, because it is an exception. */
        end
        
        /* Actually do the issue. */
        always @(posedge clk)
        begin
                cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
-               cpsr_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_cpsr;
+               cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
                regs_inflight[0] <= regs_inflight[1];
-               regs_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_regs;
+               regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
+               
+               if (waiting)
+               begin
+                       $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
+               end
 
                outbubble <= inbubble | waiting | !condition_met;
                outpc <= inpc;
                outinsn <= insn;
-               outstall <= waiting && !inbubble;
        end
 endmodule