+ /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
+ `DECODE_LDMSTM: if(!inbubble) begin
+ outstall = rw_wait;
+ next_outbubble = rw_wait;
+ case(lsm_state)
+ 3'b001: begin
+// next_regs = insn[23] ? op1[15:0] : op1[0:15];
+ /** verilator can suck my dick */
+ next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
+ op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
+ offset = 6'b0;
+ outstall = 1'b1;
+ next_lsm_state = 3'b010;
+ end
+ 3'b010: begin
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+ casez(regs)
+ 16'b???????????????1: begin
+ cur_reg = 4'h0;
+ next_regs = {regs[15:1], 1'b0};
+ end
+ 16'b??????????????10: begin
+ cur_reg = 4'h1;
+ next_regs = {regs[15:2], 2'b0};
+ end
+ 16'b?????????????100: begin
+ cur_reg = 4'h2;
+ next_regs = {regs[15:3], 3'b0};
+ end
+ 16'b????????????1000: begin
+ cur_reg = 4'h3;
+ next_regs = {regs[15:4], 4'b0};
+ end
+ 16'b???????????10000: begin
+ cur_reg = 4'h4;
+ next_regs = {regs[15:5], 5'b0};
+ end
+ 16'b??????????100000: begin
+ cur_reg = 4'h5;
+ next_regs = {regs[15:6], 6'b0};
+ end
+ 16'b?????????1000000: begin
+ cur_reg = 4'h6;
+ next_regs = {regs[15:7], 7'b0};
+ end
+ 16'b????????10000000: begin
+ cur_reg = 4'h7;
+ next_regs = {regs[15:8], 8'b0};
+ end
+ 16'b???????100000000: begin
+ cur_reg = 4'h8;
+ next_regs = {regs[15:9], 9'b0};
+ end
+ 16'b??????1000000000: begin
+ cur_reg = 4'h9;
+ next_regs = {regs[15:10], 10'b0};
+ end
+ 16'b?????10000000000: begin
+ cur_reg = 4'hA;
+ next_regs = {regs[15:11], 11'b0};
+ end
+ 16'b????100000000000: begin
+ cur_reg = 4'hB;
+ next_regs = {regs[15:12], 12'b0};
+ end
+ 16'b???1000000000000: begin
+ cur_reg = 4'hC;
+ next_regs = {regs[15:13], 13'b0};
+ end
+ 16'b??10000000000000: begin
+ cur_reg = 4'hD;
+ next_regs = {regs[15:14], 14'b0};
+ end
+ 16'b?100000000000000: begin
+ cur_reg = 4'hE;
+ next_regs = {regs[15], 15'b0};
+ end
+ 16'b1000000000000000: begin
+ cur_reg = 4'hF;
+ next_regs = 16'b0;
+ end
+ default: begin
+ cur_reg = 4'hx;
+ next_regs = 16'b0;
+ end
+ endcase
+ cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
+ if(cur_reg == 4'hF && insn[22]) begin
+ next_outcpsr = spsr;
+ end
+
+ if(rw_wait) begin
+ next_regs = regs;
+ cur_reg = prev_reg;
+ raddr = prev_raddr;
+ end
+ else begin
+ offset = prev_offset + 6'h4;
+ offset_sel = insn[24] ? offset : prev_offset;
+ raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+ if(insn[20]) begin
+ next_write_reg = 1'b1;
+ next_write_num = cur_reg;
+ next_write_data = rd_data;
+ end
+ end
+
+ st_read = cur_reg;
+ wr_data = st_data;
+ busaddr = {raddr[31:2], 2'b0};
+
+ outstall = 1'b1;
+
+ if(next_regs == 16'b0) begin
+ next_lsm_state = 3'b100;
+ end
+ end
+ 3'b100: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
+ next_lsm_state = 3'b001;
+ end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDCSTC: if(!inbubble) begin
+ $display("WARNING: Unimplemented LDCSTC");
+ end
+ `DECODE_CDP: if(!inbubble) begin
+ cp_req = 1;
+ if (cp_busy) begin
+ outstall = 1;
+ next_outbubble = 1;
+ end
+ if (!cp_ack) begin
+ /* XXX undefined instruction trap */
+ $display("WARNING: Possible CDP undefined instruction");
+ end
+ end
+ `DECODE_MRCMCR: if(!inbubble) begin
+ cp_req = 1;
+ cp_rnw = insn[20] /* L */;
+ if (insn[20] == 0 /* store to coprocessor */)
+ cp_write = op0;
+ else begin
+ if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[15:12];
+ next_write_data = cp_read;
+ end else
+ next_outcpsr = {cp_read[31:28], cpsr[27:0]};
+ end
+ if (cp_busy) begin
+ outstall = 1;
+ next_outbubble = 1;
+ end
+ if (!cp_ack) begin
+ $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
+ end
+ $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);