Memory: wire -> reg in some cases
[firearm.git] / Memory.v
index bfec0c0..241c50a 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -4,6 +4,8 @@ module Memory(
        input clk,
        input Nrst,
 
+       input flush,
+
        /* bus interface */
        output reg [31:0] busaddr,
        output reg rd_req,
@@ -21,7 +23,7 @@ module Memory(
        output reg cp_req,
        input cp_ack,
        input cp_busy,
-       output cp_rnw,  /* 1 = read from CP, 0 = write to CP */
+       output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
        input [31:0] cp_read,
        output reg [31:0] cp_write,
        
@@ -46,8 +48,8 @@ module Memory(
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
-       output reg [31:0] out_spsr = 32'hxxxxxxxx,
-       output reg [31:0] out_cpsr = 32'hxxxxxxxx
+       output reg [31:0] outspsr = 32'hxxxxxxxx,
+       output reg [31:0] outcpsr = 32'hxxxxxxxx
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
@@ -55,10 +57,10 @@ module Memory(
        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback;
 
-       wire next_outbubble;    
-       wire next_write_reg;
-       wire [3:0] next_write_num;
-       wire [31:0] next_write_data;
+       reg next_outbubble;     
+       reg next_write_reg;
+       reg [3:0] next_write_num;
+       reg [31:0] next_write_data;
 
        reg [1:0] lsr_state = 2'b01, next_lsr_state;
        reg [31:0] align_s1, align_s2, align_rddata;
@@ -87,8 +89,8 @@ module Memory(
                prev_reg <= cur_reg;
                prev_offset <= offset;
                prev_raddr <= raddr;
-               out_cpsr <= next_outcpsr;
-               out_spsr <= spsr;
+               outcpsr <= next_outcpsr;
+               outspsr <= spsr;
                swp_state <= next_swp_state;
                lsm_state <= next_lsm_state;
                lsr_state <= next_lsr_state;
@@ -115,7 +117,7 @@ module Memory(
                cp_rnw = 1'bx;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
-               next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+               next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
                lsrh_rddata = 32'hxxxxxxxx;
                lsrh_rddata_s1 = 16'hxxxx;
                lsrh_rddata_s2 = 8'hxx;
@@ -127,7 +129,9 @@ module Memory(
                cur_reg = prev_reg;
 
                /* XXX shit not given about endianness */
-               casez(insn)
+               if (flush)
+                       next_outbubble = 1'b1;
+               else casez(insn)
                `DECODE_ALU_SWP: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
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