input [31:0] insn,
input [31:0] inpc,
input [31:0] incpsr,
+ input [31:0] inspsr,
output reg [31:0] op0,
output reg [31:0] op1,
output reg [31:0] op2,
output reg carry,
+ output reg [31:0] outspsr,
output reg [3:0] read_0,
output reg [3:0] read_1,
`DECODE_CDP, /* Coprocessor data op */
`DECODE_MRCMCR, /* Coprocessor register transfer */
`DECODE_SWI: /* SWI */
- rpc = inpc - 8;
+ rpc = inpc + 8;
`DECODE_ALU: /* ALU */
- rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+ rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
default: /* X everything else out */
rpc = 32'hxxxxxxxx;
endcase
begin
read_0 = insn[19:16]; /* Rn */
read_1 = insn[3:0]; /* Rm */
+ read_2 = insn[15:12];
op0_out = regs0;
if(insn[25]) begin
op1_out = shift_res;
carry_out = shift_cflag_out;
end
+ op2_out = regs2;
end
`DECODE_LDMSTM: /* Block data transfer */
begin
op1 <= op1_out; /* 'operand 2' - Rm */
op2 <= op2_out; /* thirdedge - Rs */
carry <= carry_out;
+ outspsr <= inspsr;
end
endmodule