+ wire [31:0] rotate_res;
+
+ assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
+ assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
+ assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
+
+ IREALLYHATEARMSHIFT shift(.insn(insn),
+ .operand(regs1),
+ .reg_amt(regs2),
+ .cflag_in(incpsr[`CPSR_C]),
+ .res(shift_res),
+ .cflag_out(shift_cflag_out));
+
+ SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
+ .amt(insn[11:8]),
+ .res(rotate_res));
+
+ always @(*)
+ casez (insn)
+ `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+// `DECODE_ALU_MUL_LONG, /* Multiply long */
+ `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
+ `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
+ `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ `DECODE_ALU_SWP, /* Atomic swap */
+ `DECODE_ALU_BX, /* Branch and exchange */
+ `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
+ `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
+ `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
+ `DECODE_LDRSTR, /* Single data transfer */
+ `DECODE_LDMSTM, /* Block data transfer */
+ `DECODE_BRANCH, /* Branch */
+ `DECODE_LDCSTC, /* Coprocessor data transfer */
+ `DECODE_CDP, /* Coprocessor data op */
+ `DECODE_SWI: /* SWI */
+ rpc = inpc + 8;
+ `DECODE_MRCMCR: /* Coprocessor register transfer */
+ rpc = inpc + 12;
+ `DECODE_ALU: /* ALU */
+ rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
+ default: /* X everything else out */
+ rpc = 32'hxxxxxxxx;
+ endcase
+
+ always @(*) begin
+ read_0 = 4'hx;
+ read_1 = 4'hx;
+ read_2 = 4'hx;
+
+ op0_out = 32'hxxxxxxxx;
+ op1_out = 32'hxxxxxxxx;
+ op2_out = 32'hxxxxxxxx;
+ carry_out = 1'bx;
+
+ casez (insn)
+ `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+ begin
+ read_0 = insn[15:12]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ read_2 = insn[11:8]; /* Rs */
+
+ op0_out = regs0;
+ op1_out = regs1;
+ op2_out = regs2;
+ end
+// `DECODE_ALU_MUL_LONG: /* Multiply long */
+// begin
+// read_0 = insn[11:8]; /* Rn */
+// read_1 = insn[3:0]; /* Rm */
+// read_2 = 4'b0; /* anyus */
+//
+// op1_res = regs1;
+// end
+ `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
+ begin end
+ `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
+ begin
+ read_0 = insn[3:0]; /* Rm */
+
+ op0_out = regs0;
+ end
+ `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ begin
+ read_0 = insn[3:0]; /* Rm */
+
+ if(insn[25]) begin /* the constant case */
+ op0_out = rotate_res;
+ end else begin
+ op0_out = regs0;
+ end
+ end
+ `DECODE_ALU_SWP: /* Atomic swap */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+
+ op0_out = regs0;
+ op1_out = regs1;
+ end
+ `DECODE_ALU_BX: /* Branch and exchange */
+ begin
+ read_0 = insn[3:0]; /* Rn */
+
+ op0_out = regs0;
+ end
+ `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
+ begin
+ read_0 = insn[19:16];
+ read_1 = insn[3:0];
+ read_2 = insn[15:12];