+// `DECODE_ALU_MUL_LONG: /* Multiply long */
+// read_0 = insn[11:8]; /* Rn */
+// read_1 = insn[3:0]; /* Rm */
+// read_2 = 4'b0; /* anyus */
+ `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
+ begin end
+ `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
+ `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ read_0 = insn[3:0]; /* Rm */
+ `DECODE_ALU_SWP: /* Atomic swap */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ end
+ `DECODE_ALU_BX: /* Branch and exchange */
+ read_0 = insn[3:0]; /* Rn */
+ `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
+ begin
+ read_0 = insn[19:16];
+ read_1 = insn[3:0];
+ end
+ `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
+ begin
+ read_0 = insn[19:16];
+ end
+ `DECODE_ALU: /* ALU */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ read_2 = insn[11:8]; /* Rs for shift */
+ end
+ `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
+ begin end
+ `DECODE_LDRSTR: /* Single data transfer */
+ begin
+ read_0 = insn[19:16]; /* Rn */
+ read_1 = insn[3:0]; /* Rm */
+ end
+ `DECODE_LDMSTM: /* Block data transfer */
+ read_0 = insn[19:16];
+ `DECODE_BRANCH: /* Branch */
+ begin end
+ `DECODE_LDCSTC: /* Coprocessor data transfer */
+ read_0 = insn[19:16];
+ `DECODE_CDP: /* Coprocessor data op */
+ begin end
+ `DECODE_MRCMCR: /* Coprocessor register transfer */
+ read_0 = insn[15:12];
+ `DECODE_SWI: /* SWI */
+ begin end
+ default:
+ $display("Undecoded instruction");
+ endcase
+ end
+
+ always @(*) begin
+ op0_out = 32'hxxxxxxxx;
+ op1_out = 32'hxxxxxxxx;
+ op2_out = 32'hxxxxxxxx;
+ carry_out = 1'bx;
+ casez (insn)
+ `DECODE_ALU_MULT: begin /* Multiply */
+ op0_out = regs0;
+ op1_out = regs1;
+ op2_out = regs2;
+ end
+// `DECODE_ALU_MULT_LONG: begin /* Multiply long */
+// op1_res = regs1;
+// end
+ `DECODE_ALU_MRS: begin /* MRS (Transfer PSR to register) */
+ end
+ `DECODE_ALU_MSR: begin /* MSR (Transfer register to PSR) */
+ op0_out = regs0;