Add skeleton to Execute.v

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index 4865aa359bd262ceabc18a21bcae8e098698fcfe..6be1af5c17fb63c10d351ada86270371cdbd8181 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -16,6 +16,7 @@ module Execute(
        
        output reg outstall = 0,
        output reg outbubble = 1,
+       output reg [31:0] outcpsr = 0,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx
@@ -26,10 +27,47 @@ module Execute(
        wire mult_done;
        wire [31:0] mult_result;
        
+       reg [31:0] alu_in0, alu_in1;
+       reg [3:0] alu_op;
+       reg alu_setflags;
+       wire [31:0] alu_result, alu_outcpsr;
+       wire alu_set;
+       
        Multiplier multiplier(
                .clk(clk), .Nrst(Nrst),
                .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
                .in1(mult_in1), .done(mult_done), .result(mult_result));
+       
+       ALU alu(
+               .clk(clk), .Nrst(Nrst),
+               .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
+               .setflags(alu_setflags), .shifter_carry(carry),
+               .result(alu_result), .cpsr_out(alu_outcpsr), .set(alu_set));
+
+       always @(*)
+               casez (insn)
+               `DECODE_ALU_MULT,       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+//             `DECODE_ALU_MUL_LONG,   /* Multiply long */
+               `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
+               `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
+               `DECODE_ALU_MSR_FLAGS,  /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               `DECODE_ALU_SWP,        /* Atomic swap */
+               `DECODE_ALU_BX,         /* Branch */
+               `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
+               `DECODE_ALU_HDATA_IMM,  /* Halfword transfer - immediate offset */
+               `DECODE_ALU,            /* ALU */
+               `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
+               `DECODE_LDRSTR,         /* Single data transfer */
+               `DECODE_LDMSTM,         /* Block data transfer */
+               `DECODE_BRANCH,         /* Branch */
+               `DECODE_LDCSTC,         /* Coprocessor data transfer */
+               `DECODE_CDP,            /* Coprocessor data op */
+               `DECODE_MRCMCR,         /* Coprocessor register transfer */
+               `DECODE_SWI:            /* SWI */
+               begin end
+               default:                /* X everything else out */
+               begin end
+               endcase
 endmodule
 
 module Multiplier(
@@ -123,15 +161,15 @@ module ALU(
                        setres = 1'b1;
                end
                `ALU_ADC: begin
-                       {flag_c, res} = sum + cpsr[`CPSR_C];
+                       {flag_c, res} = sum + {32'b0, cpsr[`CPSR_C]};
                        setres = 1'b1;
                end
                `ALU_SBC: begin
-                       {flag_c, res} = diff - (~cpsr[`CPSR_C]);
+                       {flag_c, res} = diff - {32'b0, (~cpsr[`CPSR_C])};
                        setres = 1'b1;
                end
                `ALU_RSC: begin
-                       {flag_c, res} = rdiff - (~cpsr[`CPSR_C]);
+                       {flag_c, res} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
                        setres = 1'b1;
                end
                `ALU_TST: begin