Add special CPSR behavior for ARM MCR.
[firearm.git] / RegFile.v
index f5a63ae..1e94174 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -6,6 +6,9 @@ module RegFile(
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,
+       input [3:0] read_3,
+       output reg [31:0] rdata_3,
+       output reg [31:0] spsr,
        input [3:0] write,
        input write_req,
        input [31:0] write_data
@@ -22,14 +25,14 @@ module RegFile(
                regfile[4'h5] = 32'h00500000;
                regfile[4'h6] = 32'h05000000;
                regfile[4'h7] = 32'h50000000;
-               regfile[4'h8] = 32'h0000000A;
-               regfile[4'h9] = 32'h000000A0;
-               regfile[4'hA] = 32'h00000A00;
-               regfile[4'hB] = 32'h0000A000;
-               regfile[4'hC] = 32'h000A0000;
-               regfile[4'hD] = 32'h00A00000;
-               regfile[4'hE] = 32'h0A000000;
-               regfile[4'hF] = 32'hA0000000;
+               regfile[4'h8] = 32'hA0000000;
+               regfile[4'h9] = 32'h0A000000;
+               regfile[4'hA] = 32'h00A00000;
+               regfile[4'hB] = 32'h000A0000;
+               regfile[4'hC] = 32'h0000A000;
+               regfile[4'hD] = 32'h00000A00;
+               regfile[4'hE] = 32'h000000A0;
+               regfile[4'hF] = 32'h00000000;   /* Start off claiming we are in user mode. */
        end
        
        always @(*)
@@ -48,6 +51,13 @@ module RegFile(
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
+
+               if ((read_3 == write) && write_req)
+                       rdata_3 = write_data;
+               else
+                       rdata_3 = regfile[read_3];
+               
+               spsr = regfile[4'hF];
        end
        
        always @(posedge clk)
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