32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
32'b????00010?00????????00001001????, /* Atomic swap */
- 32'b????000100101111111111110001????, /* Branch */
+ 32'b????000100101111111111110001????, /* Branch and exchange */
32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
32'b????011????????????????????1????, /* Undefined. I hate ARM */
rpc = 32'hxxxxxxxx;
endcase
- always @ (*) begin
+ always @(*)
casez (insn)
- 32'b????000000??????????????1001????: begin /* Multiply */
+ 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
read_0 = insn[15:12]; /* Rn */
+// 32'b????00001???????????????1001????, /* Multiply long */
+// read_0 = insn[11:8]; /* Rn */
+ 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
+ 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
+ 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ read_0 = 4'hx;
+ 32'b????00??????????????????????????: /* ALU */
+ read_0 = insn[19:16]; /* Rn */
+ 32'b????00010?00????????00001001????: /* Atomic swap */
+ read_0 = insn[19:16]; /* Rn */
+ 32'b????000100101111111111110001????: /* Branch and exchange */
+ read_0 = insn[3:0]; /* Rn */
+ 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
+ read_0 = insn[19:16];
+ 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */
+ read_0 = insn[19:16];
+ 32'b????011????????????????????1????: /* Undefined. I hate ARM */
+ read_0 = 4'hx;
+ 32'b????01??????????????????????????: /* Single data transfer */
+ read_0 = insn[19:16]; /* Rn */
+ 32'b????100?????????????????????????: /* Block data transfer */
+ read_0 = insn[19:16];
+ 32'b????101?????????????????????????: /* Branch */
+ read_0 = 4'hx;
+ 32'b????110?????????????????????????: /* Coprocessor data transfer */
+ read_0 = insn[19:16];
+ 32'b????1110???????????????????0????, /* Coprocessor data op */
+ 32'b????1110???????????????????1????, /* Coprocessor register transfer */
+ 32'b????1111????????????????????????: /* SWI */
+ read_0 = 4'hx;
+ default:
+ read_0 = 4'hx;
+ endcase
+
+ always @(*)
+ casez (insn)
+ 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+ read_1 = insn[3:0]; /* Rm */
+// 32'b????00001???????????????1001????: /* Multiply long */
+// read_1 = insn[3:0]; /* Rm */
+ 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
+ 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
+ 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ read_1 = 4'hx;
+ 32'b????00??????????????????????????: /* ALU */
+ read_1 = insn[3:0]; /* Rm */
+ 32'b????00010?00????????00001001????: /* Atomic swap */
read_1 = insn[3:0]; /* Rm */
+ 32'b????000100101111111111110001????: /* Branch and exchange */
+ read_1 = 4'hx;
+ 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
+ read_1 = insn[3:0];
+ 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */
+ read_1 = insn[3:0];
+ 32'b????011????????????????????1????: /* Undefined. I hate ARM */
+ read_1 = 4'hx;
+ 32'b????01??????????????????????????: /* Single data transfer */
+ read_1 = insn[3:0]; /* Rm */
+ 32'b????100?????????????????????????, /* Block data transfer */
+ 32'b????101?????????????????????????, /* Branch */
+ 32'b????110?????????????????????????, /* Coprocessor data transfer */
+ 32'b????1110???????????????????0????, /* Coprocessor data op */
+ 32'b????1110???????????????????1????, /* Coprocessor register transfer */
+ 32'b????1111????????????????????????: /* SWI */
+ read_1 = 4'hx;
+ default:
+ read_1 = 4'hx;
+ endcase
+
+ always @(*)
+ casez (insn)
+ 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
read_2 = insn[11:8]; /* Rs */
+// 32'b????00001???????????????1001????: /* Multiply long */
+// read_2 = 4'b0; /* anyus */
+ 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
+ 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
+ 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ read_2 = 4'hx;
+ 32'b????00??????????????????????????: /* ALU */
+ read_2 = insn[11:8]; /* Rs for shift */
+ 32'b????00010?00????????00001001????, /* Atomic swap */
+ 32'b????000100101111111111110001????, /* Branch and exchange */
+ 32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
+ 32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
+ 32'b????011????????????????????1????, /* Undefined. I hate ARM */
+ 32'b????01??????????????????????????, /* Single data transfer */
+ 32'b????100?????????????????????????, /* Block data transfer */
+ 32'b????101?????????????????????????, /* Branch */
+ 32'b????110?????????????????????????, /* Coprocessor data transfer */
+ 32'b????1110???????????????????0????, /* Coprocessor data op */
+ 32'b????1110???????????????????1????, /* Coprocessor register transfer */
+ 32'b????1111????????????????????????: /* SWI */
+ read_2 = 4'hx;
+ default:
+ read_2 = 4'hx;
+ endcase
+
+ always @ (*) begin
+ op1_res = 32'hxxxxxxxx;
+ cpsr = 32'hxxxxxxxx;
+ casez (insn)
+ 32'b????000000??????????????1001????: begin /* Multiply */
op1_res = regs1;
cpsr = incpsr;
end
-/*
- 32'b????00001???????????????1001????: begin * Multiply long *
- read_0 = insn[11:8]; * Rn *
- read_1 = insn[3:0]; * Rm *
- read_2 = 4'b0; * anyus *
- op1_res = regs1;
- end
-*/
+// 32'b????00001???????????????1001????: begin /* Multiply long */
+// op1_res = regs1;
+// end
32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
cpsr = incpsr;
end
cpsr = incpsr;
end
32'b????00??????????????????????????: begin /* ALU */
- read_0 = insn[19:16]; /* Rn */
- read_1 = insn[3:0]; /* Rm */
- read_2 = insn[11:8]; /* Rs for shift */
if(insn[25]) begin /* the constant case */
cpsr = incpsr;
op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
end
end
32'b????00010?00????????00001001????: begin /* Atomic swap */
- read_0 = insn[19:16]; /* Rn */
- read_1 = insn[3:0]; /* Rm */
- read_2 = 4'b0; /* anyus */
op1_res = regs1;
end
32'b????000100101111111111110001????: begin /* Branch and exchange */
- read_0 = insn[3:0]; /* Rn */
cpsr = incpsr;
end
32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
- read_0 = insn[19:16];
- read_1 = insn[3:0];
- read_2 = 4'b0;
op1_res = regs1;
cpsr = incpsr;
end
32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
- read_0 = insn[19:16];
- read_1 = insn[3:0];
op1_res = {24'b0, insn[11:8], insn[3:0]};
cpsr = incpsr;
end
/* eat shit */
end
32'b????01??????????????????????????: begin /* Single data transfer */
- read_0 = insn[19:16]; /* Rn */
- read_1 = insn[3:0]; /* Rm */
if(insn[25]) begin
op1_res = {20'b0, insn[11:0]};
cpsr = incpsr;
end
end
32'b????100?????????????????????????: begin /* Block data transfer */
- read_0 = insn[19:16];
op1_res = {16'b0, insn[15:0]};
cpsr = incpsr;
end
cpsr = incpsr;
end
32'b????110?????????????????????????: begin /* Coprocessor data transfer */
- read_0 = insn[19:16];
op1_res = {24'b0, insn[7:0]};
cpsr = incpsr;
end
git.joshuawise.com / firearm.git / blobdiff