+ end
+ `DECODE_LDMSTM: /* Block data transfer */
+ read_0 = insn[19:16];
+ `DECODE_BRANCH: /* Branch */
+ begin end
+ `DECODE_LDCSTC: /* Coprocessor data transfer */
+ read_0 = insn[19:16];
+ `DECODE_CDP: /* Coprocessor data op */
+ begin end
+ `DECODE_MRCMCR: /* Coprocessor register transfer */
+ read_0 = insn[15:12];
+ `DECODE_SWI: /* SWI */
+ begin end
+ default:
+ $display("Undecoded instruction");
+ endcase
+ end
+
+ always @(*) begin
+ op0_out = 32'hxxxxxxxx;
+ op1_out = 32'hxxxxxxxx;
+ op2_out = 32'hxxxxxxxx;
+ carry_out = 1'bx;
+ casez (insn)
+ `DECODE_ALU_MULT: begin /* Multiply */
+ op0_out = regs0;
+ op1_out = regs1;
+ op2_out = regs2;
+ end
+// `DECODE_ALU_MULT_LONG: begin /* Multiply long */
+// op1_res = regs1;
+// end
+ `DECODE_ALU_MRS: begin /* MRS (Transfer PSR to register) */
+ end
+ `DECODE_ALU_MSR: begin /* MSR (Transfer register to PSR) */
+ op0_out = regs0;
+ end
+ `DECODE_ALU_MSR_FLAGS: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ if(insn[25]) begin /* the constant case */
+ op0_out = rotate_res;
+ end else begin
+ op0_out = regs0;
+ end
+ end
+ `DECODE_ALU_SWP: begin /* Atomic swap */
+ op0_out = regs0;
+ op1_out = regs1;
+ end
+ `DECODE_ALU_BX: begin /* Branch and exchange */
+ op0_out = regs0;
+ end
+ `DECODE_ALU_HDATA_REG: begin /* Halfword transfer - register offset */
+ op0_out = regs0;
+ op1_out = regs1;
+ end
+ `DECODE_ALU_HDATA_IMM: begin /* Halfword transfer - immediate offset */
+ op0_out = regs0;
+ op1_out = {24'b0, insn[11:8], insn[3:0]};
+ end
+ `DECODE_ALU: begin /* ALU */
+ op0_out = regs0;
+ if(insn[25]) begin /* the constant case */
+ carry_out = incpsr[`CPSR_C];
+ op1_out = rotate_res;
+ end else begin
+ carry_out = shift_cflag_out;
+ op1_out = shift_res;
+ end
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin /* Undefined. I hate ARM */
+ /* eat shit */
+ end
+ `DECODE_LDRSTR: begin /* Single data transfer */
+ op0_out = regs0;