output reg [3:0] write_num = 4'bxxxx,
output reg [31:0] write_data = 32'hxxxxxxxx,
output reg [31:0] jmppc,
- output reg jmp
+ output reg jmp,
+ output reg [31:0] outpc,
+ output reg [31:0] outinsn,
+ output reg [31:0] outop0, outop1, outop2
);
reg mult_start;
write_reg <= next_write_reg;
write_num <= next_write_num;
write_data <= next_write_data;
+ outpc <= pc;
+ outinsn <= insn;
+ outop0 <= op0;
+ outop1 <= op1;
+ outop2 <= op2;
end
end
alu_setflags = 1'bx;
jmp = 1'b0;
- jmppc = 32'hxxxxxxxx;
+ jmppc = 32'h00000000;
casez (insn)
`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
begin end
`DECODE_BRANCH:
begin
- if(!inbubble) begin
+ if(!inbubble && !flush) begin
jmppc = pc + op0 + 32'h8;
if(insn[24]) begin
next_write_reg = 1;
next_write_num = 4'hE; /* link register */
- next_write_data = pc - 32'h4;
+ next_write_data = pc + 32'h4;
end
jmp = 1'b1;
end