Memory: Add delayed flush. Make outbubble correct by moving it to the end (sadface...

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index 8a7d8f62a210b73e4f32ad0837a5f8d30d332398..ac828a5ea5f1111c0fba6a0af766c888ae0d9000 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -23,7 +23,10 @@ module Execute(
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,
        output reg [31:0] jmppc,
-       output reg jmp
+       output reg jmp,
+       output reg [31:0] outpc,
+       output reg [31:0] outinsn,
+       output reg [31:0] outop0, outop1, outop2
        );
        
        reg mult_start;
@@ -54,7 +57,7 @@ module Execute(
                .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
                .setflags(alu_setflags), .shifter_carry(carry),
                .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
-       
+
        always @(posedge clk)
        begin
                if (!stall)
@@ -65,8 +68,20 @@ module Execute(
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
+                       outpc <= pc;
+                       outinsn <= insn;
+                       outop0 <= op0;
+                       outop1 <= op1;
+                       outop2 <= op2;
                end
        end
+       
+       reg delayedflush = 0;
+       always @(posedge clk)
+               if (flush && outstall /* halp! I can't do it now, maybe later? */)
+                       delayedflush <= 1;
+               else if (!outstall /* anything has been handled this time around */)
+                       delayedflush <= 0;
 
        reg prevstall = 0;
        always @(posedge clk)
@@ -75,7 +90,7 @@ module Execute(
        always @(*)
        begin
                outstall = stall;
-               next_outbubble = inbubble | flush;
+               next_outbubble = inbubble | flush | delayedflush;
                next_outcpsr = cpsr;
                next_outspsr = spsr;
                next_write_reg = 0;
@@ -93,7 +108,7 @@ module Execute(
                alu_setflags = 1'bx;
 
                jmp = 1'b0;
-               jmppc = 32'hxxxxxxxx;
+               jmppc = 32'h00000000;
 
                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
@@ -106,8 +121,8 @@ module Execute(
                                mult_in1 = op2 /* Rs */;
                                $display("New MUL instruction");
                        end
-                       outstall = stall | ((!prevstall | !mult_done) && !inbubble);
-                       next_outbubble = inbubble | !mult_done | !prevstall;
+                       outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
+                       next_outbubble = next_outbubble | !mult_done | !prevstall;
                        next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
                        next_write_reg = 1;
                        next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
@@ -163,12 +178,12 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
-                       if(!inbubble) begin
+                       if(!inbubble && !flush && !delayedflush) begin
                                jmppc = pc + op0 + 32'h8;
                                if(insn[24]) begin
                                        next_write_reg = 1;
                                        next_write_num = 4'hE; /* link register */
-                                       next_write_data = pc - 32'h4;
+                                       next_write_data = pc + 32'h4;
                                end
                                jmp = 1'b1;
                        end