module Decode(
input clk,
+ input stall,
input [31:0] insn,
input [31:0] inpc,
input [31:0] incpsr,
output reg [31:0] op1,
output reg [31:0] op2,
output reg carry,
+ output reg [31:0] outcpsr,
output reg [31:0] outspsr,
output reg [3:0] read_0,
read_2 = insn[15:12];
op0_out = regs0;
- if(insn[25]) begin
+ if(!insn[25] /* immediate */) begin
op1_out = {20'b0, insn[11:0]};
carry_out = incpsr[`CPSR_C];
end else begin
always @ (posedge clk) begin
- op0 <= op0_out; /* Rn - always */
- op1 <= op1_out; /* 'operand 2' - Rm */
- op2 <= op2_out; /* thirdedge - Rs */
- carry <= carry_out;
- outspsr <= inspsr;
+ if (!stall)
+ begin
+ op0 <= op0_out; /* Rn - always */
+ op1 <= op1_out; /* 'operand 2' - Rm */
+ op2 <= op2_out; /* thirdedge - Rs */
+ carry <= carry_out;
+ outcpsr <= incpsr;
+ outspsr <= inspsr;
+ end
end
endmodule