+ always @(posedge clk)
+ begin
+ outpc <= pc;
+ outinsn <= insn;
+ outbubble <= next_outbubble;
+ out_write_reg <= next_write_reg;
+ out_write_num <= next_write_num;
+ out_write_data <= next_write_data;
+ if (!rw_wait)
+ prev_offset <= offset;
+ prev_raddr <= raddr;
+ outcpsr <= next_outcpsr;
+ outspsr <= spsr;
+ outcpsrup <= next_outcpsrup;
+ swp_state <= next_swp_state;
+ lsm_state <= next_lsm_state;
+ lsr_state <= next_lsr_state;
+ lsrh_state <= next_lsrh_state;
+ if (do_rd_data_latch)
+ rd_data_latch <= rd_data;
+ swp_oldval <= next_swp_oldval;
+ prevaddr <= addr;
+ end
+
+ reg delayedflush = 0;
+ always @(posedge clk)
+ if (flush && outstall /* halp! I can't do it now, maybe later? */)
+ delayedflush <= 1;
+ else if (!outstall /* anything has been handled this time around */)
+ delayedflush <= 0;
+
+ /* Drive the state machines and stall. */
+ always @(*)
+ begin
+ outstall = 1'b0;
+ next_lsm_state = lsm_state;
+ next_lsr_state = lsr_state;
+ next_lsrh_state = lsrh_state;
+ next_swp_state = swp_state;
+ casez(insn)
+ `DECODE_ALU_SWP: if(!inbubble) begin
+ case(swp_state)
+ `SWP_READING: begin
+ outstall = 1'b1;
+ if (!rw_wait)
+ next_swp_state = `SWP_WRITING;
+ $display("SWP: read stage");
+ end
+ `SWP_WRITING: begin
+ outstall = rw_wait;
+ if(!rw_wait)
+ next_swp_state = `SWP_READING;
+ $display("SWP: write stage");
+ end
+ default: begin
+ outstall = 1'bx;
+ next_swp_state = 2'bxx;
+ end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin
+ outstall = 1'b0; /* XXX work around for Xilinx bug */
+ next_lsrh_state = lsrh_state;
+ end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
+ case(lsrh_state)
+ `LSRH_MEMIO: begin
+ outstall = rw_wait;
+ if(insn[21] | !insn[24]) begin
+ outstall = 1'b1;
+ if(!rw_wait)
+ next_lsrh_state = `LSRH_BASEWB;
+ end
+
+ if (flush) /* special case! */ begin
+ outstall = 1'b0;
+ next_lsrh_state = `LSRH_MEMIO;
+ end
+
+ $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
+ end
+ `LSRH_BASEWB: begin
+ outstall = 1'b1;
+ next_lsrh_state = `LSRH_WBFLUSH;
+ end
+ `LSRH_WBFLUSH: begin
+ outstall = 1'b0;
+ next_lsrh_state = `LSRH_MEMIO;
+ end
+ default: begin
+ outstall = 1'bx;
+ next_lsrh_state = 3'bxxx;
+ end
+ endcase
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!inbubble) begin
+ outstall = rw_wait;
+ case(lsr_state)
+ `LSR_MEMIO: begin
+ outstall = rw_wait;
+ next_lsr_state = `LSR_MEMIO;
+ if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */
+ outstall = 1'b1;
+ if (!rw_wait)
+ next_lsr_state = `LSR_STRB_WR;
+ end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */
+ outstall = 1'b1;
+ if (!rw_wait)
+ next_lsr_state = `LSR_BASEWB;
+ end
+
+ if (flush) begin
+ outstall = 1'b0;
+ next_lsr_state = `LSR_MEMIO;
+ end
+ $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
+ end
+ `LSR_STRB_WR: begin
+ outstall = 1;
+ if(insn[21] /* W */ | !insn[24] /* P */) begin
+ if(!rw_wait)
+ next_lsr_state = `LSR_BASEWB;
+ end else if (!rw_wait)
+ next_lsr_state = `LSR_WBFLUSH;
+ $display("LDRSTR: Handling STRB");
+ end
+ `LSR_BASEWB: begin
+ outstall = 1;
+ next_lsr_state = `LSR_WBFLUSH;
+ end
+ `LSR_WBFLUSH: begin
+ outstall = 0;
+ next_lsr_state = `LSR_MEMIO;
+ end
+ default: begin
+ outstall = 1'bx;
+ next_lsr_state = 4'bxxxx;
+ end
+ endcase
+ $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
+ end
+ `DECODE_LDMSTM: if(!inbubble) begin
+ outstall = rw_wait;
+ case(lsm_state)
+ `LSM_SETUP: begin
+ outstall = 1'b1;
+ next_lsm_state = `LSM_MEMIO;
+ if (flush) begin
+ outstall = 1'b0;
+ next_lsm_state = `LSM_SETUP;
+ end
+ $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
+ end
+ `LSM_MEMIO: begin
+ outstall = 1'b1;
+ if(next_regs == 16'b0 && !rw_wait) begin
+ next_lsm_state = `LSM_BASEWB;
+ end
+
+ $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, st_data, busaddr);
+ end
+ `LSM_BASEWB: begin
+ outstall = 1;
+ next_lsm_state = `LSM_WBFLUSH;
+ $display("LDMSTM: Stage 3: Writing back");
+ end
+ `LSM_WBFLUSH: begin
+ outstall = 0;
+ next_lsm_state = `LSM_SETUP;
+ end
+ default: begin
+ outstall = 1'bx;
+ next_lsm_state = 4'bxxxx;
+ end
+ endcase
+ $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
+ end
+ `DECODE_LDCSTC: if(!inbubble) begin
+ $display("WARNING: Unimplemented LDCSTC");
+ end
+ `DECODE_CDP: if (!inbubble) begin
+ if (cp_busy) begin
+ outstall = 1;
+ end
+ if (!cp_ack) begin
+ /* XXX undefined instruction trap */
+ $display("WARNING: Possible CDP undefined instruction");
+ end
+ end
+ `DECODE_MRCMCR: if (!inbubble) begin
+ if (cp_busy) begin
+ outstall = 1;
+ end
+ if (!cp_ack) begin
+ $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
+ end
+ $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
+ end
+ default: begin end
+ endcase
+ end
+
+ /* Coprocessor input. */
+ always @(*)
+ begin
+ cp_req = 0;
+ cp_rnw = 1'bx;
+ cp_write = 32'hxxxxxxxx;
+ casez (insn)
+ `DECODE_CDP: if(!inbubble) begin
+ cp_req = 1;
+ end
+ `DECODE_MRCMCR: if(!inbubble) begin
+ cp_req = 1;
+ cp_rnw = insn[20] /* L */;
+ if (insn[20] == 0 /* store to coprocessor */)
+ cp_write = op0;
+ end
+ endcase
+ end
+
+ /* Register output logic. */
+ always @(*)
+ begin
+ next_write_reg = write_reg;
+ next_write_num = write_num;
+ next_write_data = write_data;
+ next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
+ next_outcpsrup = cpsrup;
+
+ casez(insn)
+ `DECODE_ALU_SWP: if (!inbubble) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(swp_state)
+ `SWP_READING:
+ next_write_reg = 1'b0;
+ `SWP_WRITING: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[15:12];
+ next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
+ end
+ default: begin end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin
+ next_write_reg = write_reg; /* XXX workaround for ISE 10.1 bug */
+ next_write_num = write_num;
+ next_write_data = write_data;
+ next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
+ next_outcpsrup = cpsrup;
+ end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(lsrh_state)
+ `LSRH_MEMIO: begin
+ next_write_num = insn[15:12];
+ next_write_data = lsrh_rddata;
+ if(insn[20]) begin
+ next_write_reg = 1'b1;
+ end
+ end
+ `LSRH_BASEWB: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = addr;
+ end
+ `LSRH_WBFLUSH:
+ next_write_reg = 1'b0;
+ default: begin end
+ endcase
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!inbubble) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(lsr_state)
+ `LSR_MEMIO: begin
+ next_write_reg = insn[20] /* L */;
+ next_write_num = insn[15:12];
+ if(insn[20] /* L */) begin
+ next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
+ end
+ end
+ `LSR_STRB_WR:
+ next_write_reg = 1'b0;
+ `LSR_BASEWB: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = addr;
+ end
+ `LSR_WBFLUSH:
+ next_write_reg = 1'b0;
+ default: begin end
+ endcase
+ end
+ `DECODE_LDMSTM: if(!inbubble) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ case(lsm_state)
+ `LSM_SETUP:
+ next_write_reg = 1'b0;
+ `LSM_MEMIO: begin
+ if(insn[20] /* L */) begin
+ next_write_reg = !rw_wait;
+ next_write_num = cur_reg;
+ next_write_data = rd_data;
+ end else
+ next_write_reg = 1'b0;
+ end
+ `LSM_BASEWB: begin
+ next_write_reg = insn[21] /* writeback */;
+ next_write_num = insn[19:16];
+ next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
+ if(cur_reg == 4'hF && insn[22]) begin
+ next_outcpsr = spsr;
+ next_outcpsrup = 1;
+ end
+ end
+ `LSM_WBFLUSH:
+ next_write_reg = 1'b0;
+ default: begin end
+ endcase
+ end
+ `DECODE_MRCMCR: if(!inbubble) begin
+ next_write_reg = 1'bx;
+ next_write_num = 4'bxxxx;
+ next_write_data = 32'hxxxxxxxx;
+ next_outcpsr = 32'hxxxxxxxx;
+ next_outcpsrup = 1'bx;
+ if (insn[20] == 1 /* load from coprocessor */)
+ if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[15:12];
+ next_write_data = cp_read;
+ end else begin
+ next_outcpsr = {cp_read[31:28], cpsr[27:0]};
+ next_outcpsrup = 1;
+ end
+ end
+ endcase
+ end
+
+ /* Bus/address control logic. */