Decode: Fix stupid bug in which stalls did not stall the decoder.
[firearm.git] / Issue.v
diff --git a/Issue.v b/Issue.v
index 4147c9f..7b281a3 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -130,18 +130,6 @@ module Issue(
                        def_cpsr = 1;
                        def_regs = 0;
                end
-               `DECODE_ALU:    /* ALU */
-               begin
-                       use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
-                       use_regs =
-                               (insn[25] /* I */ ? 0 :
-                                       (insn[4] /* shift by reg */ ?
-                                               (idxbit(rs) | idxbit(rm)) :
-                                               (idxbit(rm)))) |
-                               (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
-                       def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc);
-                       def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
-               end
                `DECODE_ALU_SWP:        /* Atomic swap */
                begin
                        use_cpsr = `COND_MATTERS(cond);
@@ -170,6 +158,18 @@ module Issue(
                        def_cpsr = 0;
                        def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
                end
+               `DECODE_ALU:    /* ALU */
+               begin
+                       use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
+                       use_regs =
+                               (insn[25] /* I */ ? 0 :
+                                       (insn[4] /* shift by reg */ ?
+                                               (idxbit(rs) | idxbit(rm)) :
+                                               (idxbit(rm)))) |
+                               (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
+                       def_cpsr = insn[20] /* S */;
+                       def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
+               end
                `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
                begin   
                        use_cpsr = 0;
@@ -282,24 +282,33 @@ module Issue(
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
                
-               outstall = waiting && !inbubble;        /* Happens in an always @*, because it is an exception. */
+               outstall = ((waiting && !inbubble) || stall) && !flush; /* Happens in an always @*, because it is an exception. */
        end
        
        /* Actually do the issue. */
        always @(posedge clk)
        begin
-               cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
-               cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
-               regs_inflight[0] <= regs_inflight[1];
-               regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
-               
                if (waiting)
-               begin
                        $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
-               end
 
-               outbubble <= inbubble | waiting | !condition_met;
-               outpc <= inpc;
-               outinsn <= insn;
+               if(flush)
+               begin
+                       cpsr_inflight[0] = 1'b0;
+                       cpsr_inflight[1] = 1'b0;
+                       regs_inflight[0] = 16'b0;
+                       regs_inflight[1] = 16'b0;
+                       outbubble <= 1'b1;
+               end
+               else if (!stall)
+               begin
+                       cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
+                       cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
+                       regs_inflight[0] <= regs_inflight[1];
+                       regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
+                       
+                       outbubble <= inbubble | waiting | !condition_met;
+                       outpc <= inpc;
+                       outinsn <= insn;
+               end
        end
 endmodule
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