initialize inflights

[firearm.git] / Issue.v

diff --git a/Issue.v b/Issue.v
index a7456568c77d0e013d56e1ddf06217f97c321944..85d1393035078ea80e66c710167b90c496734f28 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -2,7 +2,7 @@
 
 module Issue(
        input clk,
-       input Nrst,
+       input Nrst,     /* XXX not used yet */
        
        input stall,    /* pipeline control */
        input flush,
@@ -264,6 +264,14 @@ module Issue(
        reg waiting_regs;
        wire waiting = waiting_cpsr | waiting_regs;
        
+       initial
+       begin
+               cpsr_inflight[0] = 0;
+               cpsr_inflight[1] = 0;
+               regs_inflight[0] = 0;
+               regs_inflight[1] = 0;
+       end
+               
        always @(*)
        begin
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
@@ -271,19 +279,16 @@ module Issue(
        end
        
        /* Actually do the issue. */
-       always @(*)
-               outstall = waiting;
-       
        always @(posedge clk)
        begin
                cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
-               cpsr_inflight[1] <= (waiting | inbubble) ? 0 : def_cpsr;
+               cpsr_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_cpsr;
                regs_inflight[0] <= regs_inflight[1];
-               regs_inflight[1] <= (waiting | inbubble) ? 0 : def_regs;
+               regs_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_regs;
 
                outbubble <= inbubble | waiting | !condition_met;
                outpc <= inpc;
                outinsn <= insn;
+               outstall <= waiting;
        end
-       
 endmodule