tests/Makefile: Add a target to pad binaries for Xilinx tools.
[firearm.git] / Fetch.v
diff --git a/Fetch.v b/Fetch.v
index 5255647..aa9bd7c 100644 (file)
--- a/Fetch.v
+++ b/Fetch.v
@@ -14,12 +14,14 @@ module Fetch(
        output reg [31:0] insn = 0,
        output reg [31:0] pc = 32'hFFFFFFFC);
        
-       reg qjmp = 0;   /* A jump has been queued up while we were stalled. */
+       reg qjmp = 0;   /* A jump has been queued up while we were waiting. */
        reg [31:0] qjmppc;
-       always @(posedge clk)
-               if (stall && jmp && !qjmp)
+       always @(posedge clk or negedge Nrst)
+               if (!Nrst)
+                       qjmp <= 0;
+               else if ((rd_wait || stall) && jmp)
                        {qjmp,qjmppc} <= {jmp, jmppc};
-               else if (!stall && qjmp)        /* It has already been handled. */
+               else if (!rd_wait && !stall && qjmp)    /* It has already been intoed. */
                        {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
        
        reg [31:0] reqpc;
@@ -36,18 +38,10 @@ module Fetch(
        assign rd_addr = reqpc;
        assign rd_req = 1;
        
-       always @(negedge Nrst)
-       begin
-               pc <= 32'hFFFFFFFC;
-               qjmp <= 0;
-               bubble <= 1;
-       end
-       
-       always @(posedge clk)
+       always @(posedge clk or negedge Nrst)
        begin
                if (!Nrst) begin
                        pc <= 32'hFFFFFFFC;
-                       qjmp <= 0;
                        bubble <= 1;
                end else if (!stall)
                begin
This page took 0.01839 seconds and 4 git commands to generate.