if (rd_req && !cache_hit && bus_ack) begin
bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
bus_rd = 1;
if (rd_req && !cache_hit && bus_ack) begin
bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
bus_rd = 1;