- addr = insn[23] ? base + offset : base - offset; /* up/down select */
- raddr = insn[24] ? base : addr;
- busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
- rd_req = insn[20];
- wr_req = ~insn[20];
- if(!insn[20]) begin /* store */
- st_read = insn[15:12];
- wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
- end
- else if(insn[15:12] == 4'hF)
- flush = 1'b1;
- end
- `DECODE_LDMSTM: begin
- end
- default: begin end
- endcase
- end
-
- assign align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
- assign align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
- assign align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-
- always @(posedge clk)
- begin
- outpc <= pc;
- outbubble <= rw_wait;
- casez(insn)
- `DECODE_LDRSTR_UNDEFINED: begin
- writeback <= 1'b0;
- regsel <= 4'hx;
- regdata <= 32'hxxxxxxxx;
- notdone <= 1'b0;
- end
- `DECODE_LDRSTR: begin
- if(insn[20] && !inc_next) begin /* load - delegate regfile write to writeback stage */
- if(insn[15:12] == 4'hF) begin
- newpc <= align_rddata;
+ if (!inbubble) begin
+ outstall = rw_wait | notdone;
+
+ addr = insn[23] ? base + offset : base - offset; /* up/down select */
+ raddr = insn[24] ? base : addr;
+ busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+
+ /* rotate to correct position */
+ align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+ align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+ /* select byte or word */
+ align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+
+ if(!insn[20]) begin
+ st_read = insn[15:12];
+ wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */