RegFile: Move to assigns, since XST can't always @(regfile).

[firearm.git] / Issue.v

diff --git a/Issue.v b/Issue.v
index c3e579155bf09c9019a42d4df130291c9c2cf01e..792fdbd79a333476c50386219d2934875ffe858c 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -167,7 +167,7 @@ module Issue(
                                                (idxbit(rs) | idxbit(rm)) :
                                                (idxbit(rm)))) |
                                (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
                                                (idxbit(rs) | idxbit(rm)) :
                                                (idxbit(rm)))) |
                                (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);

-                       def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc);
+                       def_cpsr = insn[20] /* S */;

                        def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
                end
                `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
                        def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
                end
                `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */


@@ -180,7 +180,7 @@ module Issue(
                `DECODE_LDRSTR:
                begin
                        use_cpsr = `COND_MATTERS(cond);
                `DECODE_LDRSTR:
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
+                       use_regs = idxbit(rn) | (insn[25] /* I */ ? idxbit(rm) : 0) | (insn[20] /* L */ ? 0 : idxbit(rd));

                        def_cpsr = 0;
                        def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
                end
                        def_cpsr = 0;
                        def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
                end


@@ -196,7 +196,7 @@ module Issue(
                        use_cpsr = `COND_MATTERS(cond);
                        use_regs = 0;
                        def_cpsr = 0;
                        use_cpsr = `COND_MATTERS(cond);
                        use_regs = 0;
                        def_cpsr = 0;

-                       def_regs = 0;
+                       def_regs = insn[24] /* L */ ? (16'b1 << 14) : 0;

                end
                `DECODE_LDCSTC: /* Coprocessor data transfer */
                begin
                end
                `DECODE_LDCSTC: /* Coprocessor data transfer */
                begin


@@ -282,15 +282,22 @@ module Issue(
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
                
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
                

-               outstall = (waiting && !inbubble) || stall;     /* Happens in an always @*, because it is an exception. */
+               outstall = (waiting && !inbubble && !flush) || stall;   /* Happens in an always @*, because it is an exception. */

        end
        end

-       
+
+       reg delayedflush = 0;
+       always @(posedge clk)
+               if (flush && outstall /* halp! I can't do it now, maybe later? */)
+                       delayedflush <= 1;
+               else if (!outstall /* anything has been handled this time around */)
+                       delayedflush <= 0;
+

        /* Actually do the issue. */
        always @(posedge clk)
        begin
                if (waiting)
                        $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
        /* Actually do the issue. */
        always @(posedge clk)
        begin
                if (waiting)
                        $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);

-       
+

                if (!stall)
                begin
                        cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
                if (!stall)
                begin
                        cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */


@@ -298,7 +305,7 @@ module Issue(
                        regs_inflight[0] <= regs_inflight[1];
                        regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
                        
                        regs_inflight[0] <= regs_inflight[1];
                        regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
                        

-                       outbubble <= inbubble | waiting | !condition_met;
+                       outbubble <= inbubble | waiting | !condition_met | flush | delayedflush;

                        outpc <= inpc;
                        outinsn <= insn;
                end
                        outpc <= inpc;
                        outinsn <= insn;
                end