+ /* XXX shit not given about endianness */
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if(!bubble_3a) begin
+ next_outbubble = dc__rw_wait_3a;
+ case(swp_state)
+ `SWP_READING:
+ if(!dc__rw_wait_3a)
+ next_swp_oldval = dc__rd_data_3a;
+ `SWP_WRITING: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin
+ next_outbubble = bubble_3a; /* XXX workaround for Xilinx bug */
+ end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
+ next_outbubble = dc__rw_wait_3a;
+
+ /* rotate to correct position */
+ case(insn_3a[6:5])
+ 2'b01: begin /* unsigned half */
+ lsrh_rddata = {16'b0, raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0]};
+ end
+ 2'b10: begin /* signed byte */
+ lsrh_rddata_s1 = raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0];
+ lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
+ lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
+ end
+ 2'b11: begin /* signed half */
+ lsrh_rddata = raddr[1] ? {{16{dc__rd_data_3a[31]}}, dc__rd_data_3a[31:16]} : {{16{dc__rd_data_3a[15]}}, dc__rd_data_3a[15:0]};