- always @(posedge clk)
- if (rd_req && !cache_hit) begin
- if (bus_ready) begin /* Started the fill, and we have data. */
- cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
- cache_fill_pos <= cache_fill_pos + 1;
- if (cache_fill_pos == 15) begin /* Done? */
- cache_tags[rd_idx] <= rd_tag;
- cache_valid[rd_idx] <= 1;
- end
- end
+ always @(posedge clk) begin
+ // Do the actual read.
+ rd_data_1a <= cache_data[{rd_idx_0a,rd_didx_word_0a}];
+
+ rd_addr_1a <= {rd_addr_0a[31:6], 6'b0};
+ if (cache_fill_pos_0a != 0 && ((rd_addr_1a != {rd_addr_0a[31:6], 6'b0}) || cache_hit_0a)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+ cache_fill_pos_0a <= 0;
+ else if (rd_req_0a && !cache_hit_0a && bus_ack && bus_ready) begin
+ $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr_0a, bus_addr, bus_rdata);
+ cache_data[{rd_idx_0a,cache_fill_pos_0a}] <= bus_rdata;
+ cache_fill_pos_0a <= cache_fill_pos_0a + 1;
+ if (cache_fill_pos_0a == 15) begin /* Done? */
+ cache_tags[rd_idx_0a] <= rd_tag_0a;
+ cache_valid[rd_idx_0a] <= 1;
+ $display("ICACHE: Fill complete for line %x, tag %x", rd_idx_0a, rd_tag_0a);
+ end else
+ cache_valid[rd_idx_0a] <= 0;