output reg [31:0] rd_data,
/* bus interface */
- output reg bus_req,
+ output wire bus_req,
input bus_ack,
output reg [31:0] bus_addr,
input [31:0] bus_rdata,
reg [4:0] i;
initial
for (i = 0; i < 16; i = i + 1)
+ begin
cache_valid[i[3:0]] = 0;
+ cache_tags[i[3:0]] = 0;
+ end
wire [5:0] rd_didx = rd_addr[5:0];
wire [3:0] rd_didx_word = rd_didx[5:2];
always @(posedge clk)
if (rd_req && !cache_hit) begin
if (bus_ready) begin /* Started the fill, and we have data. */
+ $display("CACHE FILL: rq adr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
cache_fill_pos <= cache_fill_pos + 1;
if (cache_fill_pos == 15) begin /* Done? */