wire icache_rd_req;
wire icache_rd_wait;
wire [31:0] icache_rd_data;
+
+ wire stall_cause_issue;
+
+ wire stall_in_fetch = stall_cause_issue;
+ wire stall_in_issue = 0;
+
+ wire bubble_out_fetch;
+ wire bubble_out_issue;
+ wire [31:0] insn_out_fetch;
+ wire [31:0] insn_out_issue;
+ wire [31:0] pc_out_fetch;
+ wire [31:0] pc_out_issue;
+
+ assign bubbleshield = bubble_out_issue;
+ assign insn = insn_out_issue;
+ assign pc = pc_out_issue;
BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
.Nrst(1 /* XXX */),
.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
- .stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
- .bubble(bubbleshield), .insn(insn), .pc(pc));
-
+ .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
+ .bubble(bubble_out_fetch), .insn(insn_out_fetch),
+ .pc(pc_out_fetch));
+
+ Issue issue(
+ .clk(clk),
+ .Nrst(1 /* XXX */),
+ .stall(stall_in_issue), .flush(0 /* XXX */),
+ .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
+ .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
+ .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
+ .outpc(pc_out_issue), .outinsn(insn_out_issue));
+
+ always @(posedge clk)
+ begin
+ $display("Clock-time dump:");
+ $display("Fetch stage: Bubble output: %d, Instruction: %08x, PC: %08x", bubble_out_fetch, insn_out_fetch, pc_out_fetch);
+ $display("Issue stage: Stall output: %d, Bubble output: %d, Instruction: %08x, PC: %08x", stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
+ end
endmodule