Add wires for ALU.

[firearm.git] / BlockRAM.v

diff --git a/BlockRAM.v b/BlockRAM.v
index 85f865974fbd3f3bb88e13bb2d3cfe274d0b3607..1731c30363f4920a0860af2df2331e6ec00c31d5 100644 (file)
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -14,27 +14,30 @@ module BlockRAM(
         */
        wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000;
        /* verilator lint_off WIDTH */
-       wire [13:2] ramaddr = bus_addr & 32'h3FFC;      /* mask off lower two bits
+       wire [13:0] ramaddr = bus_addr & 32'h3FFC;      /* mask off lower two bits
                                                         * for word alignment */
        /* verilator lint_on WIDTH */
        
-       reg [31:0] data [0:(16384 / 4 - 1)];
+       reg [31:0] data [(16384 / 4 - 1):0];
        
-       reg [31:0] temprdata;
-       reg [13:2] lastread;
+       reg [31:0] temprdata = 0;
+       reg [13:0] lastread = 14'h3FFF;
        assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
        
        assign bus_ready = decode &&
                (bus_wr || (bus_rd && (lastread == ramaddr)));
        
+       initial
+               $readmemh("ram.hex", data);
+       
        always @(posedge clk)
        begin
                if (bus_wr && decode)
-                       data[ramaddr] <= bus_wdata;
+                       data[ramaddr[13:2]] <= bus_wdata;
                
                /* This is not allowed to be conditional -- stupid Xilinx
                 * blockram. */
-               temprdata <= data[ramaddr];
+               temprdata <= data[ramaddr[13:2]];
                lastread <= ramaddr;
        end
 endmodule