Console: Put the core in its own clock domain.
[firearm.git] / Fetch.v
diff --git a/Fetch.v b/Fetch.v
index 0a18b31..3f28453 100644 (file)
--- a/Fetch.v
+++ b/Fetch.v
@@ -10,32 +10,45 @@ module Fetch(
        input stall,
        input jmp,
        input [31:0] jmppc,
        input stall,
        input jmp,
        input [31:0] jmppc,
-       output wire bubble,
-       output wire [31:0] insn,
-       output reg [31:0] pc);
-
-       reg [31:0] prevpc;
-       initial
-               prevpc = 32'hFFFFFFFC;  /* ugh... the first pc we request will be this +4 */
-       always @(negedge Nrst)
-               prevpc <= 32'hFFFFFFFC;
+       output reg bubble = 1,
+       output reg [31:0] insn = 0,
+       output reg [31:0] pc = 32'hFFFFFFFC);
        
        
-       always @(*)
+       reg qjmp = 0;   /* A jump has been queued up while we were waiting. */
+       reg [31:0] qjmppc;
+       always @(posedge clk or negedge Nrst)
                if (!Nrst)
                if (!Nrst)
-                       pc = 32'hFFFFFFFC;
-               else if (stall) /* don't change any internal state */
-                       pc = prevpc;
-               else if (jmp)
-                       pc = jmppc;
-               else
-                       pc = prevpc + 32'h4;
+                       qjmp <= 0;
+               else if ((rd_wait || stall) && jmp)
+                       {qjmp,qjmppc} <= {jmp, jmppc};
+               else if (!rd_wait && !stall && qjmp)    /* It has already been intoed. */
+                       {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
        
        
-       assign bubble = stall | rd_wait;
-       assign rd_addr = pc;
-       assign rd_req = !stall;
-       assign insn = rd_data;
-                       
-       always @(posedge clk)
-               if (!rd_wait || !Nrst)
-                       prevpc <= pc;
+       reg [31:0] reqpc;
+       
+       /* Output latch logic */
+       assign rd_addr = reqpc;
+       assign rd_req = 1;
+       always @(posedge clk or negedge Nrst)
+               if (!Nrst) begin
+                       bubble <= 1;
+                       insn <= 0;
+                       pc <= 32'h00000000;
+               end else if (!stall) begin
+                       bubble <= (jmp || qjmp || rd_wait);
+                       insn <= rd_data;
+                       pc <= reqpc;
+               end
+       
+       always @(posedge clk or negedge Nrst)
+               if (!Nrst)
+                       reqpc <= 0;
+               else if (!stall && !rd_wait) begin
+                       if (qjmp)
+                               reqpc <= qjmppc;
+                       else if (jmp)
+                               reqpc <= jmppc;
+                       else
+                               reqpc <= reqpc + 4;
+               end
 endmodule
 endmodule
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