Console: Put the core in its own clock domain.
[firearm.git] / Memory.v
index 8a62ed1..1dad548 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -121,6 +121,7 @@ module Memory(
                lsrh_state <= next_lsrh_state;
                if (do_rd_data_latch)
                        rd_data_latch <= rd_data;
+               swp_oldval <= next_swp_oldval;
                prevaddr <= addr;
        end
        
@@ -160,7 +161,10 @@ module Memory(
                        end
                        endcase
                end
-               `DECODE_ALU_MULT: begin end
+               `DECODE_ALU_MULT: begin
+                       outstall = 1'b0;        /* XXX work around for Xilinx bug */
+                       next_lsrh_state = lsrh_state;
+               end
                `DECODE_ALU_HDATA_REG,
                `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
                        case(lsrh_state)
@@ -254,7 +258,7 @@ module Memory(
                        end
                        `LSM_MEMIO: begin
                                outstall = 1'b1;
-                               if(next_regs == 16'b0) begin
+                               if(next_regs == 16'b0 && !rw_wait) begin
                                        next_lsm_state = `LSM_BASEWB;
                                end
                                
@@ -345,7 +349,13 @@ module Memory(
                        default: begin end
                        endcase
                end
-               `DECODE_ALU_MULT: begin end
+               `DECODE_ALU_MULT: begin
+                       next_write_reg = write_reg;     /* XXX workaround for ISE 10.1 bug */
+                       next_write_num = write_num;
+                       next_write_data = write_data;
+                       next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
+                       next_outcpsrup = cpsrup;
+               end
                `DECODE_ALU_HDATA_REG,
                `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
                        next_write_reg = 1'bx;
@@ -402,7 +412,7 @@ module Memory(
                        `LSM_SETUP:
                                next_write_reg = 1'b0;
                        `LSM_MEMIO: begin
-                               if(insn[20]) begin
+                               if(insn[20] /* L */) begin
                                        next_write_reg = !rw_wait;
                                        next_write_num = cur_reg;
                                        next_write_data = rd_data;
@@ -465,7 +475,12 @@ module Memory(
                        default: begin end
                        endcase
                end
-               `DECODE_ALU_MULT: begin end
+               `DECODE_ALU_MULT: begin
+                       rd_req = 1'b0;  /* XXX workaround for Xilinx bug */
+                       wr_req = 1'b0;
+                       offset = prev_offset;
+                       addr = prevaddr;
+               end
                `DECODE_ALU_HDATA_REG,
                `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
                        addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
@@ -692,6 +707,10 @@ module Memory(
                lsrh_rddata_s1 = 16'hxxxx;
                lsrh_rddata_s2 = 8'hxx;
                next_swp_oldval = swp_oldval;
+               
+               align_s1 = 32'hxxxxxxxx;
+               align_s2 = 32'hxxxxxxxx;
+               align_rddata = 32'hxxxxxxxx;
 
                /* XXX shit not given about endianness */
                casez(insn)
@@ -705,7 +724,9 @@ module Memory(
                        default: begin end
                        endcase
                end
-               `DECODE_ALU_MULT: begin end
+               `DECODE_ALU_MULT: begin
+                       next_outbubble = inbubble;      /* XXX workaround for Xilinx bug */
+               end
                `DECODE_ALU_HDATA_REG,
                `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
                        next_outbubble = rw_wait;
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