Return decode to a state of cleanliness.
[firearm.git] / Decode.v
index fd8554b..42ae993 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -8,7 +8,7 @@ module Decode(
        output reg [31:0] op0,
        output reg [31:0] op1,
        output reg [31:0] op2,
-       output reg [31:0] outcpsr,
+       output reg carry,
 
        output [3:0] read_0,
        output [3:0] read_1,
@@ -19,7 +19,8 @@ module Decode(
        );
 
        wire [31:0] regs0, regs1, regs2, rpc;
-       wire [31:0] op1_res, cpsr;
+       wire [31:0] op0_out, op1_out, op2_out;
+       wire carry_out;
 
        /* shifter stuff */
        wire [31:0] shift_oper;
@@ -79,10 +80,11 @@ module Decode(
 //                     read_0 = insn[11:8]; /* Rn */
 //                     read_1 = insn[3:0];   /* Rm */
 //                     read_2 = 4'b0;       /* anyus */
-               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
+               begin end
                32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
                32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
-               begin end       /* Everything stays x'ed out. */
+                       read_0 = insn[3:0];     /* Rm */
                32'b????00??????????????????????????:   /* ALU */
                begin
                        read_0 = insn[19:16]; /* Rn */
@@ -104,7 +106,6 @@ module Decode(
                32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
                begin
                        read_0 = insn[19:16];
-                       read_1 = insn[3:0];
                end
                32'b????011????????????????????1????:   /* Undefined. I hate ARM */
                begin end
@@ -119,8 +120,10 @@ module Decode(
                begin end
                32'b????110?????????????????????????:   /* Coprocessor data transfer */
                        read_0 = insn[19:16];
-               32'b????1110???????????????????0????,   /* Coprocessor data op */
-               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1110???????????????????0????:   /* Coprocessor data op */
+               begin end
+               32'b????1110???????????????????1????:   /* Coprocessor register transfer */
+                       read_0 = insn[15:12];
                32'b????1111????????????????????????:   /* SWI */
                begin end
                default:
@@ -129,90 +132,96 @@ module Decode(
        end
        
        always @(*) begin
-               op1_res = 32'hxxxxxxxx;
-               cpsr = 32'hxxxxxxxx;
+               op0_out = 32'hxxxxxxxx;
+               op1_out = 32'hxxxxxxxx;
+               op2_out = 32'hxxxxxxxx;
+               carry_out = 1'bx;
                casez (insn)
                32'b????000000??????????????1001????: begin /* Multiply */
-                       op1_res = regs1;
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = regs1;
+                       op2_out = regs2;
                end
 //             32'b????00001???????????????1001????: begin /* Multiply long */
 //                     op1_res = regs1;
 //             end
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
-                       cpsr = incpsr;
                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
-                       cpsr = incpsr;
+                       op0_out = regs0;
                end
-                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
-                       cpsr = incpsr;
+                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       if(insn[25]) begin     /* the constant case */
+                               op0_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
+                       end else begin
+                               op0_out = regs0;
+                       end
                 end
                32'b????00??????????????????????????: begin /* ALU */
+                       op0_out = regs0;
                        if(insn[25]) begin     /* the constant case */
-                               cpsr = incpsr;
-                               op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
+                               carry_out = incpsr[`CPSR_C];
+                               op1_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
                        end else begin
-                               cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
-                               op1_res = shift_res;
+                               carry_out = shift_cflag_out;
+                               op1_out = shift_res;
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */
-                       op1_res = regs1;
+                       op0_out = regs0;
+                       op1_out = regs1;
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */
-                       cpsr = incpsr;
+                       op0_out = regs0;
                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
-                       op1_res = regs1;
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = regs1;
                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
-                       op1_res = {24'b0, insn[11:8], insn[3:0]};
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = {24'b0, insn[11:8], insn[3:0]};
                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */
+                       op0_out = regs0;
                        if(insn[25]) begin
-                               op1_res = {20'b0, insn[11:0]};
-                               cpsr = incpsr;
+                               op1_out = {20'b0, insn[11:0]};
+                               carry_out = incpsr[`CPSR_C];
                        end else begin
-                               op1_res = shift_res;
-                               cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
+                               op1_out = shift_res;
+                               carry_out = shift_cflag_out;
                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */
-                       op1_res = {16'b0, insn[15:0]};
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = {16'b0, insn[15:0]};
                end
                32'b????101?????????????????????????: begin /* Branch */
-                       op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
-                       cpsr = incpsr;
+                       op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */
-                       op1_res = {24'b0, insn[7:0]};
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = {24'b0, insn[7:0]};
                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */
-                       cpsr = incpsr;
                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
-                       cpsr = incpsr;
+                       op0_out = regs0;
                end
                32'b????1111????????????????????????: begin /* SWI */
-                       cpsr = incpsr;
                end
                default: begin end
                endcase
        end
 
        always @ (posedge clk) begin
-               op0 <= regs0;   /* Rn - always */
-               op1 <= op1_res; /* 'operand 2' - Rm */
-               op2 <= regs2;   /* thirdedge - Rs */
-               outcpsr <= cpsr;
+               op0 <= op0_out;   /* Rn - always */
+               op1 <= op1_out; /* 'operand 2' - Rm */
+               op2 <= op2_out;   /* thirdedge - Rs */
+               carry <= carry_out;
        end
 
 endmodule
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