if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
cache_fill_pos <= 0;
else if (rd_req && !cache_hit) begin
- if (bus_ready) begin /* Started the fill, and we have data. */
+ if (bus_ready && bus_ack) begin /* Started the fill, and we have data. */
+ $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
cache_data[idx][cache_fill_pos] <= bus_rdata;
cache_fill_pos <= cache_fill_pos + 1;
if (cache_fill_pos == 15) begin /* Done? */
cache_tags[idx] <= tag;
cache_valid[idx] <= 1;
- end
+ end else
+ cache_valid[idx] <= 0;
end
end else if (wr_req && cache_hit)
cache_data[idx][addr[5:2]] = wr_data;