+ reg [31:0] insn_2a;
+ reg stall_1a;
+ always @(posedge clk or negedge Nrst)
+ if (!Nrst) begin
+ insn_2a <= 32'h00000000;
+ stall_1a <= 0;
+ end else begin
+ insn_2a <= insn_1a;
+ stall_1a <= stall_0a;
+ end
+
+ always @(*)
+ if (stall_1a)
+ insn_1a = insn_2a;
+ else
+ insn_1a = ic__rd_data_1a;
+