Memory: Remove magic numbers from state machines.
[firearm.git] / Memory.v
index 33bd674..40e60d7 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -4,6 +4,8 @@ module Memory(
        input clk,
        input Nrst,
 
+       input flush,
+
        /* bus interface */
        output reg [31:0] busaddr,
        output reg rd_req,
@@ -11,7 +13,7 @@ module Memory(
        input rw_wait,
        output reg [31:0] wr_data,
        input [31:0] rd_data,
-       output reg [2:0] data_size;
+       output reg [2:0] data_size,
 
        /* regfile interface */
        output reg [3:0] st_read,
@@ -21,7 +23,7 @@ module Memory(
        output reg cp_req,
        input cp_ack,
        input cp_busy,
-       output cp_rnw,  /* 1 = read from CP, 0 = write to CP */
+       output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
        input [31:0] cp_read,
        output reg [31:0] cp_write,
        
@@ -34,6 +36,7 @@ module Memory(
        input [31:0] op2,
        input [31:0] spsr,
        input [31:0] cpsr,
+       input cpsrup,
        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,
@@ -46,34 +49,39 @@ module Memory(
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
-       output reg [31:0] out_spsr = 32'hxxxxxxxx,
-       output reg [31:0] out_cpsr = 32'hxxxxxxxx
+       output reg [31:0] outspsr = 32'hxxxxxxxx,
+       output reg [31:0] outcpsr = 32'hxxxxxxxx,
+       output reg outcpsrup = 1'hx
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
+       reg next_outcpsrup;
        reg [31:0] prevaddr;
        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback;
 
-       wire next_outbubble;    
-       wire next_write_reg;
-       wire [3:0] next_write_num;
-       wire [31:0] next_write_data;
+       reg next_outbubble;     
+       reg next_write_reg;
+       reg [3:0] next_write_num;
+       reg [31:0] next_write_data;
 
-       reg [1:0] lsr_state = 2'b01, next_lsr_state;
+       reg [3:0] lsr_state = 4'b0001, next_lsr_state;
        reg [31:0] align_s1, align_s2, align_rddata;
 
-       reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
+       reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
        reg [31:0] lsrh_rddata;
        reg [15:0] lsrh_rddata_s1;
        reg [7:0] lsrh_rddata_s2;
 
        reg [15:0] regs, next_regs;
-       reg [2:0] lsm_state = 3'b001, next_lsm_state;
+       reg [3:0] lsm_state = 4'b0001, next_lsm_state;
        reg [5:0] offset, prev_offset, offset_sel;
 
        reg [31:0] swp_oldval, next_swp_oldval;
        reg [1:0] swp_state = 2'b01, next_swp_state;
+       
+       reg do_rd_data_latch;
+       reg [31:0] rd_data_latch = 32'hxxxxxxxx;
 
        always @(posedge clk)
        begin
@@ -85,16 +93,27 @@ module Memory(
                out_write_data <= next_write_data;
                regs <= next_regs;
                prev_reg <= cur_reg;
-               prev_offset <= offset;
+               if (!rw_wait)
+                       prev_offset <= offset;
                prev_raddr <= raddr;
-               out_cpsr <= next_outcpsr;
-               out_spsr <= spsr;
+               outcpsr <= next_outcpsr;
+               outspsr <= spsr;
+               outcpsrup <= next_outcpsrup;
                swp_state <= next_swp_state;
                lsm_state <= next_lsm_state;
                lsr_state <= next_lsr_state;
                lsrh_state <= next_lsrh_state;
+               if (do_rd_data_latch)
+                       rd_data_latch <= rd_data;
                prevaddr <= addr;
        end
+       
+       reg delayedflush = 0;
+       always @(posedge clk)
+               if (flush && outstall /* halp! I can't do it now, maybe later? */)
+                       delayedflush <= 1;
+               else if (!outstall /* anything has been handled this time around */)
+                       delayedflush <= 0;
 
        always @(*)
        begin
@@ -106,6 +125,8 @@ module Memory(
                busaddr = 32'hxxxxxxxx;
                data_size = 3'bxxx;
                outstall = 1'b0;
+               st_read = 4'hx;
+               do_rd_data_latch = 0;
                next_write_reg = write_reg;
                next_write_num = write_num;
                next_write_data = write_data;
@@ -115,10 +136,11 @@ module Memory(
                cp_rnw = 1'bx;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
-               next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+               next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
+               next_outcpsrup = cpsrup;
                lsrh_rddata = 32'hxxxxxxxx;
-               lsrh_rddata_s1 = 32'hxxxxxxxx;
-               lsrh_rddata_s2 = 32'hxxxxxxxx;
+               lsrh_rddata_s1 = 16'hxxxx;
+               lsrh_rddata_s2 = 8'hxx;
                next_lsm_state = lsm_state;
                next_lsr_state = lsr_state;
                next_lsrh_state = lsrh_state;
@@ -126,6 +148,23 @@ module Memory(
                next_swp_state = swp_state;
                cur_reg = prev_reg;
 
+`define SWP_READING 2'b01
+`define SWP_WRITING 2'b10
+
+`define LSRH_MEMIO     3'b001
+`define LSRH_BASEWB    3'b010
+`define LSRH_WBFLUSH   3'b100
+
+`define LSR_MEMIO      4'b0001
+`define LSR_STRB_WR    4'b0010
+`define LSR_BASEWB     4'b0100
+`define LSR_WBFLUSH    4'b1000
+
+`define LSM_SETUP      4'b0001
+`define LSM_MEMIO      4'b0010
+`define LSM_BASEWB     4'b0100
+`define LSM_WBFLUSH    4'b1000
+
                /* XXX shit not given about endianness */
                casez(insn)
                `DECODE_ALU_SWP: if(!inbubble) begin
@@ -134,26 +173,29 @@ module Memory(
                        busaddr = {op0[31:2], 2'b0};
                        data_size = insn[22] ? 3'b001 : 3'b100;
                        case(swp_state)
-                       2'b01: begin
+                       `SWP_READING: begin
                                rd_req = 1'b1;
                                outstall = 1'b1;
                                if(!rw_wait) begin
-                                       next_swp_state = 2'b10;
+                                       next_swp_state = `SWP_WRITING;
                                        next_swp_oldval = rd_data;
                                end
+                               $display("SWP: read stage");
                        end
-                       2'b10: begin
+                       `SWP_WRITING: begin
                                wr_req = 1'b1;
                                wr_data = insn[22] ? {4{op1[7:0]}} : op1;
                                next_write_reg = 1'b1;
                                next_write_num = insn[15:12];
                                next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
                                if(!rw_wait)
-                                       next_swp_state = 2'b01;
+                                       next_swp_state = `SWP_READING;
+                               $display("SWP: write stage");
                        end
                        default: begin end
                        endcase
                end
+               `DECODE_ALU_MULT: begin end
                `DECODE_ALU_HDATA_REG,
                `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
                        next_outbubble = rw_wait;
@@ -163,7 +205,6 @@ module Memory(
                        busaddr = raddr;
                        /* rotate to correct position */
                        case(insn[6:5])
-                       2'b00: begin end /* swp */
                        2'b01: begin /* unsigned half */
                                wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
                                data_size = 3'b010;
@@ -181,10 +222,15 @@ module Memory(
                                data_size = 3'b010;
                                lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
                        end
+                       default: begin
+                               wr_data = 32'hxxxxxxxx;
+                               data_size = 3'bxxx;
+                               lsrh_rddata = 32'hxxxxxxxx;
+                       end
                        endcase
 
                        case(lsrh_state)
-                       2'b01: begin
+                       `LSRH_MEMIO: begin
                                rd_req = insn[20];
                                wr_req = ~insn[20];
                                next_write_num = insn[15:12];
@@ -195,55 +241,106 @@ module Memory(
                                if(insn[21] | !insn[24]) begin
                                        outstall = 1'b1;
                                        if(!rw_wait)
-                                               next_lsrh_state = 2'b10;
+                                               next_lsrh_state = `LSRH_BASEWB;
                                end
+                               $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
                        end
-                       2'b10: begin
+                       `LSRH_BASEWB: begin
+                               next_outbubble = 1'b0;
                                next_write_reg = 1'b1;
                                next_write_num = insn[19:16];
                                next_write_data = addr;
-                               next_lsrh_state = 2'b10;
+                               next_lsrh_state = `LSRH_WBFLUSH;
+                       end
+                       `LSRH_WBFLUSH: begin
+                               outstall = 0;
+                               next_lsrh_state = `LSRH_MEMIO;
                        end
                        default: begin end
                        endcase
+                       
+                       if ((lsrh_state == `LSRH_MEMIO) && flush) begin /* Reject it. */
+                               outstall = 1'b0;
+                               next_lsrh_state = `LSRH_MEMIO;
+                       end
                end
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: if(!inbubble) begin
                        next_outbubble = rw_wait;
                        outstall = rw_wait;
                        addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
-                       raddr = insn[24] ? op0 : addr; /* pre/post increment */
+                       raddr = insn[24] ? addr : op0; /* pre/post increment */
                        busaddr = raddr;
                        /* rotate to correct position */
                        align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
                        align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
                        /* select byte or word */
                        align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-                       wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+                       wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
                        data_size = insn[22] ? 3'b001 : 3'b100;
                        case(lsr_state)
-                       2'b01: begin
-                               rd_req = insn[20];
-                               wr_req = ~insn[20];
-                               next_write_reg = 1'b1;
+
+                       `LSR_MEMIO: begin
+                               rd_req = insn[20] /* L */ || insn[22] /* B */;
+                               wr_req = !insn[20] /* L */ && !insn[22]/* B */;
+                               next_write_reg = insn[20] /* L */;
                                next_write_num = insn[15:12];
-                               if(insn[20]) begin
-                                       next_write_data = align_rddata;
+                               if(insn[20] /* L */) begin
+                                       next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
                                end
-                               if(insn[21] | !insn[24]) begin
+                               if (insn[22] /* B */ && !insn[20] /* L */) begin
+                                       do_rd_data_latch = 1;
+                                       outstall = 1'b1;
+                                       if (!rw_wait)
+                                               next_lsr_state = `LSR_STRB_WR;
+                               end else if(insn[21] /* W */ | !insn[24] /* P */) begin
                                        outstall = 1'b1;
                                        if(!rw_wait)
-                                               next_lsr_state = 2'b10;
+                                               next_lsr_state = `LSR_BASEWB;
                                end
+                               $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
+                       end
+                       `LSR_STRB_WR: begin
+                               $display("LDRSTR: Handling STRB");
+                               outstall = 1;
+                               rd_req = 0;
+                               wr_req = 1;
+                               next_write_reg = 0;
+                               case (busaddr[1:0])
+                               2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
+                               2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
+                               2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
+                               2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
+                               endcase
+                               if(insn[21] /* W */ | !insn[24] /* P */) begin
+                                       if(!rw_wait)
+                                               next_lsr_state = `LSR_BASEWB;
+                               end else if (!rw_wait)
+                                       next_lsr_state = `LSR_WBFLUSH;
                        end
-                       2'b10: begin
+                       `LSR_BASEWB: begin
+                               outstall = 1;
+                               rd_req = 0;
+                               wr_req= 0;
+                               next_outbubble = 0;
                                next_write_reg = 1'b1;
                                next_write_num = insn[19:16];
                                next_write_data = addr;
-                               next_lsr_state = 2'b10;
+                               next_lsr_state = `LSR_WBFLUSH;
+                       end
+                       `LSR_WBFLUSH: begin
+                               rd_req = 0;
+                               wr_req= 0;
+                               outstall = 0;
+                               next_lsr_state = `LSR_MEMIO;
                        end
                        default: begin end
                        endcase
+                       
+                       if ((lsr_state == `LSR_MEMIO) && flush) begin   /* Reject it. */
+                               outstall = 1'b0;
+                               next_lsr_state = `LSR_MEMIO;
+                       end
                end
                /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
                `DECODE_LDMSTM: if(!inbubble) begin
@@ -251,16 +348,17 @@ module Memory(
                        next_outbubble = rw_wait;
                        data_size = 3'b100;
                        case(lsm_state)
-                       3'b001: begin
+                       `LSM_SETUP: begin
 //                             next_regs = insn[23] ? op1[15:0] : op1[0:15];
                                /** verilator can suck my dick */
-                               next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
-                                                                   op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
+                               $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
+                               next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
+                                                                           op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
                                offset = 6'b0;
                                outstall = 1'b1;
-                               next_lsm_state = 3'b010;
+                               next_lsm_state = `LSM_MEMIO;
                        end
-                       3'b010: begin
+                       4'b0010: begin
                                rd_req = insn[20];
                                wr_req = ~insn[20];
                                casez(regs)
@@ -333,45 +431,57 @@ module Memory(
                                        next_regs = 16'b0;
                                end
                                endcase
-                               cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
+                               cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
                                if(cur_reg == 4'hF && insn[22]) begin
                                        next_outcpsr = spsr;
+                                       next_outcpsrup = 1;
                                end
 
-                               if(rw_wait) begin
-                                       next_regs = regs;
-                                       cur_reg = prev_reg;
-                                       raddr = prev_raddr;
+                               offset = prev_offset + 6'h4;
+                               offset_sel = insn[24] ? offset : prev_offset;
+                               raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+                               if(insn[20]) begin
+                                       next_write_reg = !rw_wait;
+                                       next_write_num = cur_reg;
+                                       next_write_data = rd_data;
                                end
-                               else begin
-                                       offset = prev_offset + 6'h4;
-                                       offset_sel = insn[24] ? offset : prev_offset;
-                                       raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
-                                       if(insn[20]) begin
-                                               next_write_reg = 1'b1;
-                                               next_write_num = cur_reg;
-                                               next_write_data = rd_data;
-                                       end
+                               if (rw_wait) begin
+                                       next_regs = regs;
+                                       cur_reg = prev_reg;     /* whoops, do this one again */
                                end
 
                                st_read = cur_reg;
-                               wr_data = st_data;
+                               wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
                                busaddr = raddr;
+                               
+                               $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
 
                                outstall = 1'b1;
 
                                if(next_regs == 16'b0) begin
-                                       next_lsm_state = 3'b100;
+                                       next_lsm_state = `LSM_BASEWB;
                                end
                        end
-                       3'b100: begin
-                               next_write_reg = 1'b1;
+                       `LSM_BASEWB: begin
+                               outstall = 1;
+                               next_outbubble = 0;
+                               next_write_reg = insn[21] /* writeback */;
                                next_write_num = insn[19:16];
                                next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
-                               next_lsm_state = 3'b001;
+                               next_lsm_state = `LSM_WBFLUSH;
+                               $display("LDMSTM: Stage 3: Writing back");
                        end
-                       default: begin end
+                       `LSM_WBFLUSH: begin
+                               outstall = 0;
+                               next_lsm_state = `LSM_SETUP;
+                       end
+                       default: $stop;
                        endcase
+                       if ((lsm_state == `LSM_SETUP) && flush) begin   /* Reject it. */
+                               outstall = 1'b0;
+                               next_lsm_state = `LSM_SETUP;
+                       end
+                       $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
                end
                `DECODE_LDCSTC: if(!inbubble) begin
                        $display("WARNING: Unimplemented LDCSTC");
@@ -397,8 +507,10 @@ module Memory(
                                        next_write_reg = 1'b1;
                                        next_write_num = insn[15:12];
                                        next_write_data = cp_read;
-                               end else
+                               end else begin
                                        next_outcpsr = {cp_read[31:28], cpsr[27:0]};
+                                       next_outcpsrup = 1;
+                               end
                        end
                        if (cp_busy) begin
                                outstall = 1;
@@ -411,5 +523,8 @@ module Memory(
                end
                default: begin end
                endcase
+               
+               if ((flush || delayedflush) && !outstall)
+                       next_outbubble = 1'b1;
        end
 endmodule
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