Add wires for ALU.

[firearm.git] / RegFile.v

diff --git a/RegFile.v b/RegFile.v
index 47f5024f6a60c25c957c5a9d974f2936b04992b9..a9699e93ab3b49eda73685d48b155367652c8036 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -1,11 +1,11 @@
 module RegFile(
        input clk,
 module RegFile(
        input clk,

+       input [3:0] read_0,
+       output reg [31:0] rdata_0,

        input [3:0] read_1,
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,
        input [3:0] read_1,
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,

-       input [3:0] read_3,
-       output reg [31:0] rdata_3,

        input [3:0] write,
        input write_req,
        input [31:0] write_data
        input [3:0] write,
        input write_req,
        input [31:0] write_data


@@ -22,18 +22,23 @@ module RegFile(
                regfile[4'h5] = 32'h00500000;
                regfile[4'h6] = 32'h05000000;
                regfile[4'h7] = 32'h50000000;
                regfile[4'h5] = 32'h00500000;
                regfile[4'h6] = 32'h05000000;
                regfile[4'h7] = 32'h50000000;

-               regfile[4'h8] = 32'h0000000A;
-               regfile[4'h9] = 32'h000000A0;
-               regfile[4'hA] = 32'h00000A00;
-               regfile[4'hB] = 32'h0000A000;
-               regfile[4'hC] = 32'h000A0000;
-               regfile[4'hD] = 32'h00A00000;
-               regfile[4'hE] = 32'h0A000000;
-               regfile[4'hF] = 32'hA0000000;
+               regfile[4'h8] = 32'hA0000000;
+               regfile[4'h9] = 32'h0A000000;
+               regfile[4'hA] = 32'h00A00000;
+               regfile[4'hB] = 32'h000A0000;
+               regfile[4'hC] = 32'h0000A000;
+               regfile[4'hD] = 32'h00000A00;
+               regfile[4'hE] = 32'h000000A0;
+               regfile[4'hF] = 32'h0000000A;

        end
        
        always @(*)
        begin
        end
        
        always @(*)
        begin

+               if ((read_0 == write) && write_req)
+                       rdata_0 = write_data;
+               else
+                       rdata_0 = regfile[read_0];
+               

                if ((read_1 == write) && write_req)
                        rdata_1 = write_data;
                else
                if ((read_1 == write) && write_req)
                        rdata_1 = write_data;
                else


@@ -43,11 +48,6 @@ module RegFile(
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];

-               
-               if ((read_3 == write) && write_req)
-                       rdata_3 = write_data;
-               else
-                       rdata_3 = regfile[read_3];

        end
        
        always @(posedge clk)
        end
        
        always @(posedge clk)