output reg [31:0] jmppc,
output reg jmp,
output reg [31:0] outpc,
- output reg [31:0] outinsn
+ output reg [31:0] outinsn,
+ output reg [31:0] outop0, outop1, outop2
);
reg mult_start;
write_data <= next_write_data;
outpc <= pc;
outinsn <= insn;
+ outop0 <= op0;
+ outop1 <= op1;
+ outop2 <= op2;
end
end
alu_setflags = 1'bx;
jmp = 1'b0;
- jmppc = 32'hxxxxxxxx;
+ jmppc = 32'h00000000;
casez (insn)
`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */